253 lines
9.7 KiB
C
Executable File
253 lines
9.7 KiB
C
Executable File
/*******************************************************************************
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* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG
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* (now owned by Analog Devices Inc.),
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*
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* Copyright © 2024 Analog Devices Inc. All Rights Reserved.
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* This software is proprietary to Analog Devices, Inc. and its licensors.
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*******************************************************************************/
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#ifndef TMC_IC_TMC5062_H_
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#define TMC_IC_TMC5062_H_
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#include <stdint.h>
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#include <stdbool.h>
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#include <stddef.h>
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#include "TMC5062_HW_Abstraction.h"
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/*******************************************************************************
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* API Configuration Defines
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* These control optional features of the TMC-API implementation.
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* These can be commented in/out here or defined from the build system.
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*******************************************************************************/
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// Uncomment if you want to save space.....
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// and put the table into your own .c file
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//#define TMC_API_EXTERNAL_CRC_TABLE 1
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#ifndef TMC5062_CACHE
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#define TMC5062_CACHE 1
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//#define TMC5062_CACHE 0
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#endif
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// To use the caching mechanism already implemented by the TMC-API, set TMC5062_ENABLE_TMC_CACHE to '1'.
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// Set TMC5062_ENABLE_TMC_CACHE to '0' if one wants to have their own cache implementation.
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#ifndef TMC5062_ENABLE_TMC_CACHE
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#define TMC5062_ENABLE_TMC_CACHE 1
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//#define TMC5062_ENABLE_TMC_CACHE 0
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#endif
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/******************************************************************************/
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typedef enum {
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IC_BUS_SPI,
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IC_BUS_UART,
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} TMC5062BusType;
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typedef struct {
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uint32_t LUT_0; // Bits 0 - 31
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uint32_t LUT_1; // Bits 32 - 63
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uint32_t LUT_2; // Bits 64 - 95
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uint32_t LUT_3; // Bits 96 - 127
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uint32_t LUT_4; // Bits 128 - 159
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uint32_t LUT_5; // Bits 160 - 191
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uint32_t LUT_6; // Bits 192 - 223
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uint32_t LUT_7; // Bits 224 - 255
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uint8_t X1; // Segment 1
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uint8_t X2; // Segment 2
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uint8_t X3; // Segment 3
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// Segment width. Determines bit meaning (Actual bit value = (Wn - 1) + bit)
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uint8_t W0 : 2; // Segment [ 0 : X1-1]
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uint8_t W1 : 2; // Segment [X1 : X2-1]
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uint8_t W2 : 2; // Segment [X2 : X3-1]
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uint8_t W3 : 2; // Segment [X3 : 255]
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uint8_t START_SIN; // Absolute current at MSLUT[0]
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uint8_t START_SIN90; // Absolute current at MSLUT[256]
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} TMC5062_MicroStepTable;
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typedef struct
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{
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uint32_t mask;
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uint8_t shift;
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uint8_t address;
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bool isSigned;
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} RegisterField;
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// => TMC-API wrapper
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extern void tmc5062_readWriteSPI(uint16_t icID, uint8_t *data, size_t dataLength);
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extern bool tmc5062_readWriteUART(uint16_t icID, uint8_t *data, size_t writeLength, size_t readLength);
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extern TMC5062BusType tmc5062_getBusType(uint16_t icID);
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// => TMC-API wrapper
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int32_t tmc5062_readRegister(uint16_t icID, uint8_t address);
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void tmc5062_writeRegister(uint16_t icID, uint8_t address, int32_t value);
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void tmc5062_rotateMotor(uint16_t icID, uint8_t motor, int32_t velocity);
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static inline uint32_t tmc5062_fieldExtract(uint32_t data, RegisterField field)
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{
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uint32_t value = (data & field.mask) >> field.shift;
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if (field.isSigned)
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{
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// Apply signedness conversion
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uint32_t baseMask = field.mask >> field.shift;
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uint32_t signMask = baseMask & (~baseMask >> 1);
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value = (value ^ signMask) - signMask;
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}
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return value;
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}
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static inline uint32_t tmc5062_fieldRead(uint16_t icID, RegisterField field)
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{
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uint32_t value = tmc5062_readRegister(icID, field.address);
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return tmc5062_fieldExtract(value, field);
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}
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static inline uint32_t tmc5062_fieldUpdate(uint32_t data, RegisterField field, uint32_t value)
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{
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return (data & (~field.mask)) | ((value << field.shift) & field.mask);
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}
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static inline void tmc5062_fieldWrite(uint16_t icID, RegisterField field, uint32_t value)
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{
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uint32_t regValue = tmc5062_readRegister(icID, field.address);
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regValue = tmc5062_fieldUpdate(regValue, field, value);
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tmc5062_writeRegister(icID, field.address, regValue);
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}
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/**************************************************************** Cache Implementation *************************************************************************/
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#if TMC5062_CACHE == 1
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#if TMC5062_ENABLE_TMC_CACHE == 1
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// By default, support one IC in the cache
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#ifndef TMC5062_IC_CACHE_COUNT
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#define TMC5062_IC_CACHE_COUNT 1
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#endif
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typedef enum {
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TMC5062_CACHE_READ,
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TMC5062_CACHE_WRITE,
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// Special operation: Put content into the cache without marking the entry as dirty.
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// Only used to initialize the cache with hardware defaults. This will allow reading
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// from write-only registers that have a value inside them on reset. When using this
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// operation, a restore will *not* rewrite that filled register!
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TMC5062_CACHE_FILL_DEFAULT
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} TMC5062CacheOp;
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typedef struct
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{
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uint8_t address;
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uint32_t value;
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} TMC5062RegisterConstants;
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#define TMC5062_ACCESS_DIRTY 0x08 // Register has been written since reset -> shadow register is valid for restore
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#define TMC5062_ACCESS_READ 0x01
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#define TMC5062_ACCESS_W_PRESET 0x42
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#define TMC5062_IS_READABLE(x) ((x) & TMC5062_ACCESS_READ)
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#define ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0]))
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// Default Register Values
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#define R30 0x00071703 // IHOLD_IRUN
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#define R32 0x00FFFFFF // VHIGH
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#define R3A 0x00010000 // ENC_CONST
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#define R50 R30
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#define R52 R32
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#define R5A R3A
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#define R6C 0x000101D5 // CHOPCONF
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#define R7C R6C
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#define ____ 0x00
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#ifndef N_A
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#define N_A 0x00
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#endif
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static const int32_t tmc5062_sampleRegisterPreset[TMC5062_REGISTER_COUNT] = {
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// 0 1 2 3 4 5 6 7 8 9 A B C D E F
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 0x00 - 0x0F
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 0x10 - 0x1F
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 0x20 - 0x2F
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R30, 0, R32, 0, 0, 0, 0, 0, 0, 0, R3A, 0, 0, 0, 0, 0, // 0x30 - 0x3F
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 0x40 - 0x4F
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R50, 0, R52, 0, 0, 0, 0, 0, 0, 0, R5A, 0, 0, 0, 0, 0, // 0x50 - 0x5F
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N_A, N_A, N_A, N_A, N_A, N_A, N_A, N_A, N_A, N_A, 0, 0, R6C, 0, 0, 0, // 0x60 - 0x6F
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N_A, N_A, N_A, N_A, N_A, N_A, N_A, N_A, N_A, N_A, 0, 0, R7C, 0, 0, 0 // 0x70 - 0x7F
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};
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// Undefine the default register values.
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// This prevents warnings in case multiple TMC-API chip headers are included at once
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#undef R30
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#undef R32
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#undef R3A
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#undef R50
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#undef R52
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#undef R5A
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#undef R6C
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#undef R7C
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// Register access permissions:
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// 0x00: none (reserved)
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// 0x01: read
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// 0x02: write
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// 0x03: read/write
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// 0x13: read/write, separate functions/values for reading or writing
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// 0x23: read/write, flag register (write to clear)
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// 0x42: write, has hardware presets on reset
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static const uint8_t tmc5062_registerAccess[TMC5062_REGISTER_COUNT] = {
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// 0 1 2 3 4 5 6 7 8 9 A B C D E F
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0x03, 0x01, 0x01, 0x02, 0x07, 0x02, ____, ____, ____, ____, ____, ____, ____, ____, ____, ____, // 0x00 - 0x0F
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0x02, 0x01, ____, ____, ____, ____, ____, ____, 0x02, 0x01, ____, ____, ____, ____, ____, ____, // 0x10 - 0x1F
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0x03, 0x03, 0x01, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x03, ____, ____, // 0x20 - 0x2F
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0x02, 0x02, 0x02, 0x02, 0x03, 0x01, 0x01, ____, 0x03, 0x03, 0x02, 0x01, 0x01, ____, ____, ____, // 0x30 - 0x3F
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0x03, 0x03, 0x01, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x03, ____, ____, // 0x40 - 0x4F
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0x02, 0x02, 0x02, 0x02, 0x03, 0x01, 0x01, ____, 0x03, 0x03, 0x02, 0x01, 0x01, ____, ____, ____, // 0x50 - 0x5F
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0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x01, 0x01, 0x03, 0x02, 0x02, 0x01, // 0x60 - 0x6F
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0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x01, 0x01, 0x03, 0x02, 0x02, 0x01 // 0x70 - 0x7F
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};
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static const TMC5062RegisterConstants tmc5062_RegisterConstants[] =
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{ // Use ascending addresses!
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{ 0x60, 0xAAAAB554 }, // MSLUT[0]_M1
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{ 0x61, 0x4A9554AA }, // MSLUT[1]_M1
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{ 0x62, 0x24492929 }, // MSLUT[2]_M1
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{ 0x63, 0x10104222 }, // MSLUT[3]_M1
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{ 0x64, 0xFBFFFFFF }, // MSLUT[4]_M1
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{ 0x65, 0xB5BB777D }, // MSLUT[5]_M1
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{ 0x66, 0x49295556 }, // MSLUT[6]_M1
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{ 0x67, 0x00404222 }, // MSLUT[7]_M1
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{ 0x68, 0xFFFF8056 }, // MSLUTSEL_M1
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{ 0x69, 0x00F70000 }, // MSLUTSTART_M1
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{ 0x70, 0xAAAAB554 }, // MSLUT[0]_M2
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{ 0x71, 0x4A9554AA }, // MSLUT[1]_M2
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{ 0x72, 0x24492929 }, // MSLUT[2]_M2
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{ 0x73, 0x10104222 }, // MSLUT[3]_M2
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{ 0x74, 0xFBFFFFFF }, // MSLUT[4]_M2
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{ 0x75, 0xB5BB777D }, // MSLUT[5]_M2
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{ 0x76, 0x49295556 }, // MSLUT[6]_M2
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{ 0x77, 0x00404222 }, // MSLUT[7]_M2
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{ 0x78, 0xFFFF8056 }, // MSLUTSEL_M2
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{ 0x79, 0x00F70000 } // MSLUTSTART_M2
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};
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extern uint8_t tmc5062_dirtyBits[TMC5062_IC_CACHE_COUNT][TMC5062_REGISTER_COUNT/8];
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extern int32_t tmc5062_shadowRegister[TMC5062_IC_CACHE_COUNT][TMC5062_REGISTER_COUNT];
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void tmc5062_setDirtyBit(uint16_t icID, uint8_t index, bool value);
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bool tmc5062_getDirtyBit(uint16_t icID, uint8_t index);
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void tmc5062_initCache(void);
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extern bool tmc5062_cache(uint16_t icID, TMC5062CacheOp operation, uint8_t address, uint32_t *value);
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#endif
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#endif
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// => TMC-API wrapper
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/***************************************************************************************************************************************************/
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#endif /* TMC_IC_TMC5062_H_ */
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