323 lines
11 KiB
C
Executable File
323 lines
11 KiB
C
Executable File
/*******************************************************************************
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* Copyright © 2017 TRINAMIC Motion Control GmbH & Co. KG
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* (now owned by Analog Devices Inc.),
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*
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* Copyright © 2024 Analog Devices Inc. All Rights Reserved.
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* This software is proprietary to Analog Devices, Inc. and its licensors.
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*******************************************************************************/
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#include "TMC5130.h"
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#ifdef TMC_API_EXTERNAL_CRC_TABLE
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extern const uint8_t tmcCRCTable_Poly7Reflected[256];
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#else
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const uint8_t tmcCRCTable_Poly7Reflected[256] = {
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0x00, 0x91, 0xE3, 0x72, 0x07, 0x96, 0xE4, 0x75, 0x0E, 0x9F, 0xED, 0x7C, 0x09, 0x98, 0xEA, 0x7B,
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0x1C, 0x8D, 0xFF, 0x6E, 0x1B, 0x8A, 0xF8, 0x69, 0x12, 0x83, 0xF1, 0x60, 0x15, 0x84, 0xF6, 0x67,
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0x38, 0xA9, 0xDB, 0x4A, 0x3F, 0xAE, 0xDC, 0x4D, 0x36, 0xA7, 0xD5, 0x44, 0x31, 0xA0, 0xD2, 0x43,
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0x24, 0xB5, 0xC7, 0x56, 0x23, 0xB2, 0xC0, 0x51, 0x2A, 0xBB, 0xC9, 0x58, 0x2D, 0xBC, 0xCE, 0x5F,
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0x70, 0xE1, 0x93, 0x02, 0x77, 0xE6, 0x94, 0x05, 0x7E, 0xEF, 0x9D, 0x0C, 0x79, 0xE8, 0x9A, 0x0B,
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0x6C, 0xFD, 0x8F, 0x1E, 0x6B, 0xFA, 0x88, 0x19, 0x62, 0xF3, 0x81, 0x10, 0x65, 0xF4, 0x86, 0x17,
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0x48, 0xD9, 0xAB, 0x3A, 0x4F, 0xDE, 0xAC, 0x3D, 0x46, 0xD7, 0xA5, 0x34, 0x41, 0xD0, 0xA2, 0x33,
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0x54, 0xC5, 0xB7, 0x26, 0x53, 0xC2, 0xB0, 0x21, 0x5A, 0xCB, 0xB9, 0x28, 0x5D, 0xCC, 0xBE, 0x2F,
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0xE0, 0x71, 0x03, 0x92, 0xE7, 0x76, 0x04, 0x95, 0xEE, 0x7F, 0x0D, 0x9C, 0xE9, 0x78, 0x0A, 0x9B,
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0xFC, 0x6D, 0x1F, 0x8E, 0xFB, 0x6A, 0x18, 0x89, 0xF2, 0x63, 0x11, 0x80, 0xF5, 0x64, 0x16, 0x87,
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0xD8, 0x49, 0x3B, 0xAA, 0xDF, 0x4E, 0x3C, 0xAD, 0xD6, 0x47, 0x35, 0xA4, 0xD1, 0x40, 0x32, 0xA3,
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0xC4, 0x55, 0x27, 0xB6, 0xC3, 0x52, 0x20, 0xB1, 0xCA, 0x5B, 0x29, 0xB8, 0xCD, 0x5C, 0x2E, 0xBF,
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0x90, 0x01, 0x73, 0xE2, 0x97, 0x06, 0x74, 0xE5, 0x9E, 0x0F, 0x7D, 0xEC, 0x99, 0x08, 0x7A, 0xEB,
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0x8C, 0x1D, 0x6F, 0xFE, 0x8B, 0x1A, 0x68, 0xF9, 0x82, 0x13, 0x61, 0xF0, 0x85, 0x14, 0x66, 0xF7,
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0xA8, 0x39, 0x4B, 0xDA, 0xAF, 0x3E, 0x4C, 0xDD, 0xA6, 0x37, 0x45, 0xD4, 0xA1, 0x30, 0x42, 0xD3,
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0xB4, 0x25, 0x57, 0xC6, 0xB3, 0x22, 0x50, 0xC1, 0xBA, 0x2B, 0x59, 0xC8, 0xBD, 0x2C, 0x5E, 0xCF,
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};
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#endif
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/**************************************************************** Cache Implementation *************************************************************************/
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#if TMC5130_CACHE == 0
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static inline bool tmc5130_cache(uint16_t icID, TMC5130CacheOp operation, uint8_t address, uint32_t *value)
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{
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UNUSED(icID);
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UNUSED(address);
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UNUSED(operation);
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return false;
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}
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#else
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#if TMC5130_ENABLE_TMC_CACHE == 1
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uint8_t tmc5130_dirtyBits[TMC5130_IC_CACHE_COUNT][TMC5130_REGISTER_COUNT/8]= {0};
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int32_t tmc5130_shadowRegister[TMC5130_IC_CACHE_COUNT][TMC5130_REGISTER_COUNT];
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void tmc5130_setDirtyBit(uint16_t icID, uint8_t index, bool value)
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{
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if(index >= TMC5130_REGISTER_COUNT)
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return;
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uint8_t *tmp = &tmc5130_dirtyBits[icID][index / 8];
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uint8_t shift = (index % 8);
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uint8_t mask = 1 << shift;
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*tmp = (((*tmp) & (~(mask))) | (((value) << (shift)) & (mask)));
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}
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bool tmc5130_getDirtyBit(uint16_t icID, uint8_t index)
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{
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if(index >= TMC5130_REGISTER_COUNT)
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return false;
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uint8_t *tmp = &tmc5130_dirtyBits[icID][index / 8];
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uint8_t shift = (index % 8);
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return ((*tmp) >> shift) & 1;
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}
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/*
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* This function is used to cache the value written to the Write-Only registers in the form of shadow array.
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* The shadow copy is then used to read these kinds of registers.
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*/
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bool tmc5130_cache(uint16_t icID, TMC5130CacheOp operation, uint8_t address, uint32_t *value)
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{
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if (operation == TMC5130_CACHE_READ)
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{
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// Check if the value should come from cache
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// Only supported chips have a cache
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if (icID >= TMC5130_IC_CACHE_COUNT)
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return false;
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// Only non-readable registers care about caching
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// Note: This could also be used to cache i.e. RW config registers to reduce bus accesses
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if (TMC5130_IS_READABLE(tmc5130_registerAccess[address]))
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return false;
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// Grab the value from the cache
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*value = tmc5130_shadowRegister[icID][address];
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return true;
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}
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else if (operation == TMC5130_CACHE_WRITE || operation == TMC5130_CACHE_FILL_DEFAULT)
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{
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// Fill the cache
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// only supported chips have a cache
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if (icID >= TMC5130_IC_CACHE_COUNT)
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return false;
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// Write to the shadow register.
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tmc5130_shadowRegister[icID][address] = *value;
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// For write operations, mark the register dirty
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if (operation == TMC5130_CACHE_WRITE)
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{
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tmc5130_setDirtyBit(icID, address, true);
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}
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return true;
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}
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return false;
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}
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void tmc5130_initCache()
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{
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// Check if we have constants defined
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if(ARRAY_SIZE(tmc5130_RegisterConstants) == 0)
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return;
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size_t i, j, id;
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for(i = 0, j = 0; i < TMC5130_REGISTER_COUNT; i++)
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{
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// We only need to worry about hardware preset, write-only registers
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// that have not yet been written (no dirty bit) here.
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if(tmc5130_registerAccess[i] != TMC5130_ACCESS_W_PRESET)
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continue;
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// Search the constant list for the current address. With the constant
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// list being sorted in ascended order, we can walk through the list
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// until the entry with an address equal or greater than i
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while(j < ARRAY_SIZE(tmc5130_RegisterConstants) && (tmc5130_RegisterConstants[j].address < i))
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j++;
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// Abort when we reach the end of the constant list
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if (j == ARRAY_SIZE(tmc5130_RegisterConstants))
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break;
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// If we have an entry for our current address, write the constant
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if(tmc5130_RegisterConstants[j].address == i)
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{
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for (id = 0; id < TMC5130_IC_CACHE_COUNT; id++)
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{
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uint32_t temp = tmc5130_RegisterConstants[j].value;
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tmc5130_cache(id, TMC5130_CACHE_FILL_DEFAULT, i, &temp);
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}
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}
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}
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}
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#else
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// User must implement their own cache
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extern bool tmc5130_cache(uint16_t icID, TMC5130CacheOp operation, uint8_t address, uint32_t *value);
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#endif
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#endif
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/************************************************************** read / write Implementation ******************************************************************/
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static int32_t readRegisterSPI(uint16_t icID, uint8_t address);
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static void writeRegisterSPI(uint16_t icID, uint8_t address, int32_t value);
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static int32_t readRegisterUART(uint16_t icID, uint8_t registerAddress);
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static void writeRegisterUART(uint16_t icID, uint8_t registerAddress, int32_t value);
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static uint8_t CRC8(uint8_t *data, uint32_t bytes);
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// Checks which BUS type is use and then forwards it to the corresponding read function. See below.
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int32_t tmc5130_readRegister(uint16_t icID, uint8_t address)
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{
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TMC5130BusType bus = tmc5130_getBusType(icID);
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uint32_t value;
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// Read from cache for registers with write-only access
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if (tmc5130_cache(icID, TMC5130_CACHE_READ, address, &value))
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return value;
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if(bus == IC_BUS_SPI)
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{
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return readRegisterSPI(icID, address);
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}
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else if (bus == IC_BUS_UART)
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{
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return readRegisterUART(icID, address);
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}
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// ToDo: Error handling
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return -1;
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}
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// Checks which BUS type is use and then forwards it to the corresponding write function.
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void tmc5130_writeRegister(uint16_t icID, uint8_t address, int32_t value)
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{
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TMC5130BusType bus = tmc5130_getBusType(icID);
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if(bus == IC_BUS_SPI)
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{
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writeRegisterSPI(icID, address, value);
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}
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else if(bus == IC_BUS_UART)
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{
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writeRegisterUART(icID, address, value);
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}
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}
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int32_t readRegisterSPI(uint16_t icID, uint8_t address)
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{
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uint8_t data[5] = { 0 };
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// clear write bit
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data[0] = address & TMC5130_ADDRESS_MASK;
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// Send the read request
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tmc5130_readWriteSPI(icID, &data[0], sizeof(data));
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// Rewrite address and clear write bit
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data[0] = address & TMC5130_ADDRESS_MASK;
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// Send another request to receive the read reply
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tmc5130_readWriteSPI(icID, &data[0], sizeof(data));
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return ((int32_t)data[1] << 24) | ((int32_t) data[2] << 16) | ((int32_t) data[3] << 8) | ((int32_t) data[4]);
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}
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void writeRegisterSPI(uint16_t icID, uint8_t address, int32_t value)
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{
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uint8_t data[5] = { 0 };
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data[0] = address | TMC5130_WRITE_BIT;
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data[1] = 0xFF & (value>>24);
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data[2] = 0xFF & (value>>16);
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data[3] = 0xFF & (value>>8);
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data[4] = 0xFF & (value>>0);
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// Send the write request
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tmc5130_readWriteSPI(icID, &data[0], sizeof(data));
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//Cache the registers with write-only access
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tmc5130_cache(icID, TMC5130_CACHE_WRITE, address, (uint32_t *)&value);
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}
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int32_t readRegisterUART(uint16_t icID, uint8_t registerAddress)
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{
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uint8_t data[8] = { 0 };
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registerAddress = registerAddress & TMC5130_ADDRESS_MASK;
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data[0] = 0x05;
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data[1] = tmc5130_getNodeAddress(icID);
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data[2] = registerAddress;
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data[3] = CRC8(data, 3);
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if (!tmc5130_readWriteUART(icID, &data[0], 4, 8))
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return 0;
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// Byte 0: Sync nibble correct?
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if (data[0] != 0x05)
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return 0;
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// Byte 1: Master address correct?
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if (data[1] != 0xFF)
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return 0;
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// Byte 2: Address correct?
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if (data[2] != registerAddress)
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return 0;
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// Byte 7: CRC correct?
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if (data[7] != CRC8(data, 7))
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return 0;
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return ((uint32_t)data[3] << 24) | ((uint32_t)data[4] << 16) | (data[5] << 8) | data[6];
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}
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void writeRegisterUART(uint16_t icID, uint8_t registerAddress, int32_t value)
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{
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uint8_t data[8];
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data[0] = 0x05;
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data[1] = tmc5130_getNodeAddress(icID);
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data[2] = registerAddress | TMC5130_WRITE_BIT;
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data[3] = (value >> 24) & 0xFF;
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data[4] = (value >> 16) & 0xFF;
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data[5] = (value >> 8 ) & 0xFF;
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data[6] = (value ) & 0xFF;
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data[7] = CRC8(data, 7);
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tmc5130_readWriteUART(icID, &data[0], 8, 0);
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//Cache the registers with write-only access
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tmc5130_cache(icID, TMC5130_CACHE_WRITE, registerAddress, (uint32_t *)&value);
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}
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static uint8_t CRC8(uint8_t *data, uint32_t bytes)
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{
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uint8_t result = 0;
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while(bytes--)
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result = tmcCRCTable_Poly7Reflected[result ^ *data++];
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// Flip the result around
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// swap odd and even bits
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result = ((result >> 1) & 0x55) | ((result & 0x55) << 1);
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// swap consecutive pairs
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result = ((result >> 2) & 0x33) | ((result & 0x33) << 2);
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// swap nibbles ...
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result = ((result >> 4) & 0x0F) | ((result & 0x0F) << 4);
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return result;
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}
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void tmc5130_rotateMotor(uint16_t icID, uint8_t motor, int32_t velocity)
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{
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if(motor >= TMC5130_MOTORS)
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return;
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tmc5130_writeRegister(icID, TMC5130_VMAX, (velocity >= 0)? velocity : -velocity);
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// Set direction
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tmc5130_writeRegister(icID, TMC5130_RAMPMODE, (velocity >= 0) ? TMC5130_MODE_VELPOS : TMC5130_MODE_VELNEG);
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}
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/*******************************************************************************************************************************************************************/
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