413 lines
29 KiB
C
Executable File
413 lines
29 KiB
C
Executable File
/*******************************************************************************
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* Copyright © 2019 TRINAMIC Motion Control GmbH & Co. KG
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* (now owned by Analog Devices Inc.),
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*
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* Copyright © 2024 Analog Devices Inc. All Rights Reserved.
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* This software is proprietary to Analog Devices, Inc. and its licensors.
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*******************************************************************************/
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// Autogenerated C header for register fields in MAX22200
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// Generator version: 1.0
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#ifndef MAX22200_FIELDS
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#define MAX22200_FIELDS
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// Register definitions
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#define MAX22200_STATUS 0x00
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#define MAX22200_CFG_CH_0 0x01
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#define MAX22200_CFG_CH_1 0x02
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#define MAX22200_CFG_CH_2 0x03
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#define MAX22200_CFG_CH_3 0x04
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#define MAX22200_CFG_CH_4 0x05
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#define MAX22200_CFG_CH_5 0x06
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#define MAX22200_CFG_CH_6 0x07
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#define MAX22200_CFG_CH_7 0x08
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#define MAX22200_FAULT 0x09
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#define MAX22200_CFG_DPM 0x0A
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// Field definitions
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#define MAX22200_ACTIVE_MASK 0x00000001
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#define MAX22200_ACTIVE_SHIFT 0
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#define MAX22200_ACTIVE_FIELD ((RegisterField) {MAX22200_ACTIVE_MASK, MAX22200_ACTIVE_SHIFT, MAX22200_STATUS, false})
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#define MAX22200_UVM_MASK 0x00000002
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#define MAX22200_UVM_SHIFT 1
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#define MAX22200_UVM_FIELD ((RegisterField) {MAX22200_UVM_MASK, MAX22200_UVM_SHIFT, MAX22200_STATUS, false})
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#define MAX22200_COMER_MASK 0x00000004
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#define MAX22200_COMER_SHIFT 2
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#define MAX22200_COMER_FIELD ((RegisterField) {MAX22200_COMER_MASK, MAX22200_COMER_SHIFT, MAX22200_STATUS, false})
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#define MAX22200_DPM_MASK 0x00000008
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#define MAX22200_DPM_SHIFT 3
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#define MAX22200_DPM_FIELD ((RegisterField) {MAX22200_DPM_MASK, MAX22200_DPM_SHIFT, MAX22200_STATUS, false})
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#define MAX22200_HHF_MASK 0x00000010
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#define MAX22200_HHF_SHIFT 4
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#define MAX22200_HHF_FIELD ((RegisterField) {MAX22200_HHF_MASK, MAX22200_HHF_SHIFT, MAX22200_STATUS, false})
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#define MAX22200_OLF_MASK 0x00000020
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#define MAX22200_OLF_SHIFT 5
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#define MAX22200_OLF_FIELD ((RegisterField) {MAX22200_OLF_MASK, MAX22200_OLF_SHIFT, MAX22200_STATUS, false})
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#define MAX22200_OCP_MASK 0x00000040
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#define MAX22200_OCP_SHIFT 6
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#define MAX22200_OCP_FIELD ((RegisterField) {MAX22200_OCP_MASK, MAX22200_OCP_SHIFT, MAX22200_STATUS, false})
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#define MAX22200_OVT_MASK 0x00000080
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#define MAX22200_OVT_SHIFT 7
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#define MAX22200_OVT_FIELD ((RegisterField) {MAX22200_OVT_MASK, MAX22200_OVT_SHIFT, MAX22200_STATUS, false})
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#define MAX22200_CM10_MASK 0x00000300
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#define MAX22200_CM10_SHIFT 8
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#define MAX22200_CM10_FIELD ((RegisterField) {MAX22200_CM10_MASK, MAX22200_CM10_SHIFT, MAX22200_STATUS, false})
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#define MAX22200_CM32_MASK 0x00000C00
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#define MAX22200_CM32_SHIFT 10
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#define MAX22200_CM32_FIELD ((RegisterField) {MAX22200_CM32_MASK, MAX22200_CM32_SHIFT, MAX22200_STATUS, false})
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#define MAX22200_CM54_MASK 0x00003000
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#define MAX22200_CM54_SHIFT 12
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#define MAX22200_CM54_FIELD ((RegisterField) {MAX22200_CM54_MASK, MAX22200_CM54_SHIFT, MAX22200_STATUS, false})
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#define MAX22200_CM76_MASK 0x0000C000
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#define MAX22200_CM76_SHIFT 14
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#define MAX22200_CM76_FIELD ((RegisterField) {MAX22200_CM76_MASK, MAX22200_CM76_SHIFT, MAX22200_STATUS, false})
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#define MAX22200_FREQM_MASK 0x00010000
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#define MAX22200_FREQM_SHIFT 16
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#define MAX22200_FREQM_FIELD ((RegisterField) {MAX22200_FREQM_MASK, MAX22200_FREQM_SHIFT, MAX22200_STATUS, false})
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#define MAX22200_M_UVM_MASK 0x00020000
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#define MAX22200_M_UVM_SHIFT 17
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#define MAX22200_M_UVM_FIELD ((RegisterField) {MAX22200_M_UVM_MASK, MAX22200_M_UVM_SHIFT, MAX22200_STATUS, false})
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#define MAX22200_M_COMF_MASK 0x00040000
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#define MAX22200_M_COMF_SHIFT 18
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#define MAX22200_M_COMF_FIELD ((RegisterField) {MAX22200_M_COMF_MASK, MAX22200_M_COMF_SHIFT, MAX22200_STATUS, false})
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#define MAX22200_M_DPM_MASK 0x00080000
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#define MAX22200_M_DPM_SHIFT 19
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#define MAX22200_M_DPM_FIELD ((RegisterField) {MAX22200_M_DPM_MASK, MAX22200_M_DPM_SHIFT, MAX22200_STATUS, false})
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#define MAX22200_M_HHF_MASK 0x00100000
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#define MAX22200_M_HHF_SHIFT 20
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#define MAX22200_M_HHF_FIELD ((RegisterField) {MAX22200_M_HHF_MASK, MAX22200_M_HHF_SHIFT, MAX22200_STATUS, false})
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#define MAX22200_M_OLF_MASK 0x00200000
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#define MAX22200_M_OLF_SHIFT 21
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#define MAX22200_M_OLF_FIELD ((RegisterField) {MAX22200_M_OLF_MASK, MAX22200_M_OLF_SHIFT, MAX22200_STATUS, false})
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#define MAX22200_M_OCP_MASK 0x00400000
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#define MAX22200_M_OCP_SHIFT 22
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#define MAX22200_M_OCP_FIELD ((RegisterField) {MAX22200_M_OCP_MASK, MAX22200_M_OCP_SHIFT, MAX22200_STATUS, false})
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#define MAX22200_M_OVT_MASK 0x00800000
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#define MAX22200_M_OVT_SHIFT 23
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#define MAX22200_M_OVT_FIELD ((RegisterField) {MAX22200_M_OVT_MASK, MAX22200_M_OVT_SHIFT, MAX22200_STATUS, false})
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#define MAX22200_ONCH_MASK 0xFF000000
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#define MAX22200_ONCH_SHIFT 24
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#define MAX22200_ONCH_FIELD ((RegisterField) {MAX22200_ONCH_MASK, MAX22200_ONCH_SHIFT, MAX22200_STATUS, false})
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#define MAX22200_HHF_EN0_MASK 0x00000001
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#define MAX22200_HHF_EN0_SHIFT 0
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#define MAX22200_HHF_EN0_FIELD ((RegisterField) {MAX22200_HHF_EN0_MASK, MAX22200_HHF_EN0_SHIFT, MAX22200_CFG_CH_0, false})
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#define MAX22200_DPM_EN0_MASK 0x00000002
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#define MAX22200_DPM_EN0_SHIFT 1
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#define MAX22200_DPM_EN0_FIELD ((RegisterField) {MAX22200_DPM_EN0_MASK, MAX22200_DPM_EN0_SHIFT, MAX22200_CFG_CH_0, false})
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#define MAX22200_OL_EN0_MASK 0x00000004
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#define MAX22200_OL_EN0_SHIFT 2
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#define MAX22200_OL_EN0_FIELD ((RegisterField) {MAX22200_OL_EN0_MASK, MAX22200_OL_EN0_SHIFT, MAX22200_CFG_CH_0, false})
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#define MAX22200_SRC0_MASK 0x00000008
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#define MAX22200_SRC0_SHIFT 3
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#define MAX22200_SRC0_FIELD ((RegisterField) {MAX22200_SRC0_MASK, MAX22200_SRC0_SHIFT, MAX22200_CFG_CH_0, false})
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#define MAX22200_FREQ_CFG0_MASK 0x00000030
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#define MAX22200_FREQ_CFG0_SHIFT 4
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#define MAX22200_FREQ_CFG0_FIELD ((RegisterField) {MAX22200_FREQ_CFG0_MASK, MAX22200_FREQ_CFG0_SHIFT, MAX22200_CFG_CH_0, false})
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#define MAX22200_HSNLS0_MASK 0x00000040
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#define MAX22200_HSNLS0_SHIFT 6
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#define MAX22200_HSNLS0_FIELD ((RegisterField) {MAX22200_HSNLS0_MASK, MAX22200_HSNLS0_SHIFT, MAX22200_CFG_CH_0, false})
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#define MAX22200_VDRNCDR0_MASK 0x00000080
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#define MAX22200_VDRNCDR0_SHIFT 7
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#define MAX22200_VDRNCDR0_FIELD ((RegisterField) {MAX22200_VDRNCDR0_MASK, MAX22200_VDRNCDR0_SHIFT, MAX22200_CFG_CH_0, false})
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#define MAX22200_HIT_T0_MASK 0x0000FF00
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#define MAX22200_HIT_T0_SHIFT 8
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#define MAX22200_HIT_T0_FIELD ((RegisterField) {MAX22200_HIT_T0_MASK, MAX22200_HIT_T0_SHIFT, MAX22200_CFG_CH_0, false})
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#define MAX22200_HIT0_MASK 0x007F0000
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#define MAX22200_HIT0_SHIFT 16
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#define MAX22200_HIT0_FIELD ((RegisterField) {MAX22200_HIT0_MASK, MAX22200_HIT0_SHIFT, MAX22200_CFG_CH_0, false})
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#define MAX22200_TRGNSPI0_MASK 0x00800000
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#define MAX22200_TRGNSPI0_SHIFT 23
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#define MAX22200_TRGNSPI0_FIELD ((RegisterField) {MAX22200_TRGNSPI0_MASK, MAX22200_TRGNSPI0_SHIFT, MAX22200_CFG_CH_0, false})
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#define MAX22200_HOLD0_MASK 0x7F000000
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#define MAX22200_HOLD0_SHIFT 24
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#define MAX22200_HOLD0_FIELD ((RegisterField) {MAX22200_HOLD0_MASK, MAX22200_HOLD0_SHIFT, MAX22200_CFG_CH_0, false})
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#define MAX22200_HFS0_MASK 0x80000000
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#define MAX22200_HFS0_SHIFT 31
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#define MAX22200_HFS0_FIELD ((RegisterField) {MAX22200_HFS0_MASK, MAX22200_HFS0_SHIFT, MAX22200_CFG_CH_0, false})
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#define MAX22200_HHF_EN1_MASK 0x00000001
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#define MAX22200_HHF_EN1_SHIFT 0
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#define MAX22200_HHF_EN1_FIELD ((RegisterField) {MAX22200_HHF_EN1_MASK, MAX22200_HHF_EN1_SHIFT, MAX22200_CFG_CH_1, false})
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#define MAX22200_DPM_EN1_MASK 0x00000002
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#define MAX22200_DPM_EN1_SHIFT 1
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#define MAX22200_DPM_EN1_FIELD ((RegisterField) {MAX22200_DPM_EN1_MASK, MAX22200_DPM_EN1_SHIFT, MAX22200_CFG_CH_1, false})
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#define MAX22200_OL_EN1_MASK 0x00000004
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#define MAX22200_OL_EN1_SHIFT 2
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#define MAX22200_OL_EN1_FIELD ((RegisterField) {MAX22200_OL_EN1_MASK, MAX22200_OL_EN1_SHIFT, MAX22200_CFG_CH_1, false})
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#define MAX22200_SRC1_MASK 0x00000008
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#define MAX22200_SRC1_SHIFT 3
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#define MAX22200_SRC1_FIELD ((RegisterField) {MAX22200_SRC1_MASK, MAX22200_SRC1_SHIFT, MAX22200_CFG_CH_1, false})
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#define MAX22200_FREQ_CFG1_MASK 0x00000030
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#define MAX22200_FREQ_CFG1_SHIFT 4
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#define MAX22200_FREQ_CFG1_FIELD ((RegisterField) {MAX22200_FREQ_CFG1_MASK, MAX22200_FREQ_CFG1_SHIFT, MAX22200_CFG_CH_1, false})
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#define MAX22200_HSNLS1_MASK 0x00000040
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#define MAX22200_HSNLS1_SHIFT 6
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#define MAX22200_HSNLS1_FIELD ((RegisterField) {MAX22200_HSNLS1_MASK, MAX22200_HSNLS1_SHIFT, MAX22200_CFG_CH_1, false})
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#define MAX22200_VDRNCDR1_MASK 0x00000080
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#define MAX22200_VDRNCDR1_SHIFT 7
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#define MAX22200_VDRNCDR1_FIELD ((RegisterField) {MAX22200_VDRNCDR1_MASK, MAX22200_VDRNCDR1_SHIFT, MAX22200_CFG_CH_1, false})
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#define MAX22200_HIT_T1_MASK 0x0000FF00
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#define MAX22200_HIT_T1_SHIFT 8
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#define MAX22200_HIT_T1_FIELD ((RegisterField) {MAX22200_HIT_T1_MASK, MAX22200_HIT_T1_SHIFT, MAX22200_CFG_CH_1, false})
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#define MAX22200_HIT1_MASK 0x007F0000
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#define MAX22200_HIT1_SHIFT 16
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#define MAX22200_HIT1_FIELD ((RegisterField) {MAX22200_HIT1_MASK, MAX22200_HIT1_SHIFT, MAX22200_CFG_CH_1, false})
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#define MAX22200_TRGNSPI1_MASK 0x00800000
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#define MAX22200_TRGNSPI1_SHIFT 23
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#define MAX22200_TRGNSPI1_FIELD ((RegisterField) {MAX22200_TRGNSPI1_MASK, MAX22200_TRGNSPI1_SHIFT, MAX22200_CFG_CH_1, false})
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#define MAX22200_HOLD1_MASK 0x7F000000
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#define MAX22200_HOLD1_SHIFT 24
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#define MAX22200_HOLD1_FIELD ((RegisterField) {MAX22200_HOLD1_MASK, MAX22200_HOLD1_SHIFT, MAX22200_CFG_CH_1, false})
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#define MAX22200_HFS1_MASK 0x80000000
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#define MAX22200_HFS1_SHIFT 31
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#define MAX22200_HFS1_FIELD ((RegisterField) {MAX22200_HFS1_MASK, MAX22200_HFS1_SHIFT, MAX22200_CFG_CH_1, false})
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#define MAX22200_HHF_EN2_MASK 0x00000001
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#define MAX22200_HHF_EN2_SHIFT 0
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#define MAX22200_HHF_EN2_FIELD ((RegisterField) {MAX22200_HHF_EN2_MASK, MAX22200_HHF_EN2_SHIFT, MAX22200_CFG_CH_2, false})
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#define MAX22200_DPM_EN2_MASK 0x00000002
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#define MAX22200_DPM_EN2_SHIFT 1
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#define MAX22200_DPM_EN2_FIELD ((RegisterField) {MAX22200_DPM_EN2_MASK, MAX22200_DPM_EN2_SHIFT, MAX22200_CFG_CH_2, false})
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#define MAX22200_OL_EN2_MASK 0x00000004
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#define MAX22200_OL_EN2_SHIFT 2
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#define MAX22200_OL_EN2_FIELD ((RegisterField) {MAX22200_OL_EN2_MASK, MAX22200_OL_EN2_SHIFT, MAX22200_CFG_CH_2, false})
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#define MAX22200_SRC2_MASK 0x00000008
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#define MAX22200_SRC2_SHIFT 3
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#define MAX22200_SRC2_FIELD ((RegisterField) {MAX22200_SRC2_MASK, MAX22200_SRC2_SHIFT, MAX22200_CFG_CH_2, false})
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#define MAX22200_FREQ_CFG2_MASK 0x00000030
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#define MAX22200_FREQ_CFG2_SHIFT 4
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#define MAX22200_FREQ_CFG2_FIELD ((RegisterField) {MAX22200_FREQ_CFG2_MASK, MAX22200_FREQ_CFG2_SHIFT, MAX22200_CFG_CH_2, false})
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#define MAX22200_HSNLS2_MASK 0x00000040
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#define MAX22200_HSNLS2_SHIFT 6
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#define MAX22200_HSNLS2_FIELD ((RegisterField) {MAX22200_HSNLS2_MASK, MAX22200_HSNLS2_SHIFT, MAX22200_CFG_CH_2, false})
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#define MAX22200_VDRNCDR2_MASK 0x00000080
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#define MAX22200_VDRNCDR2_SHIFT 7
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#define MAX22200_VDRNCDR2_FIELD ((RegisterField) {MAX22200_VDRNCDR2_MASK, MAX22200_VDRNCDR2_SHIFT, MAX22200_CFG_CH_2, false})
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#define MAX22200_HIT_T2_MASK 0x0000FF00
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#define MAX22200_HIT_T2_SHIFT 8
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#define MAX22200_HIT_T2_FIELD ((RegisterField) {MAX22200_HIT_T2_MASK, MAX22200_HIT_T2_SHIFT, MAX22200_CFG_CH_2, false})
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#define MAX22200_HIT2_MASK 0x007F0000
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#define MAX22200_HIT2_SHIFT 16
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#define MAX22200_HIT2_FIELD ((RegisterField) {MAX22200_HIT2_MASK, MAX22200_HIT2_SHIFT, MAX22200_CFG_CH_2, false})
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#define MAX22200_TRGNSPI2_MASK 0x00800000
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#define MAX22200_TRGNSPI2_SHIFT 23
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#define MAX22200_TRGNSPI2_FIELD ((RegisterField) {MAX22200_TRGNSPI2_MASK, MAX22200_TRGNSPI2_SHIFT, MAX22200_CFG_CH_2, false})
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#define MAX22200_HOLD2_MASK 0x7F000000
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#define MAX22200_HOLD2_SHIFT 24
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#define MAX22200_HOLD2_FIELD ((RegisterField) {MAX22200_HOLD2_MASK, MAX22200_HOLD2_SHIFT, MAX22200_CFG_CH_2, false})
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#define MAX22200_HFS2_MASK 0x80000000
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#define MAX22200_HFS2_SHIFT 31
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#define MAX22200_HFS2_FIELD ((RegisterField) {MAX22200_HFS2_MASK, MAX22200_HFS2_SHIFT, MAX22200_CFG_CH_2, false})
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#define MAX22200_HHF_EN3_MASK 0x00000001
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#define MAX22200_HHF_EN3_SHIFT 0
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#define MAX22200_HHF_EN3_FIELD ((RegisterField) {MAX22200_HHF_EN3_MASK, MAX22200_HHF_EN3_SHIFT, MAX22200_CFG_CH_3, false})
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#define MAX22200_DPM_EN3_MASK 0x00000002
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#define MAX22200_DPM_EN3_SHIFT 1
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#define MAX22200_DPM_EN3_FIELD ((RegisterField) {MAX22200_DPM_EN3_MASK, MAX22200_DPM_EN3_SHIFT, MAX22200_CFG_CH_3, false})
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#define MAX22200_OL_EN3_MASK 0x00000004
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#define MAX22200_OL_EN3_SHIFT 2
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#define MAX22200_OL_EN3_FIELD ((RegisterField) {MAX22200_OL_EN3_MASK, MAX22200_OL_EN3_SHIFT, MAX22200_CFG_CH_3, false})
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#define MAX22200_SRC3_MASK 0x00000008
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#define MAX22200_SRC3_SHIFT 3
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#define MAX22200_SRC3_FIELD ((RegisterField) {MAX22200_SRC3_MASK, MAX22200_SRC3_SHIFT, MAX22200_CFG_CH_3, false})
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#define MAX22200_FREQ_CFG3_MASK 0x00000030
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#define MAX22200_FREQ_CFG3_SHIFT 4
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#define MAX22200_FREQ_CFG3_FIELD ((RegisterField) {MAX22200_FREQ_CFG3_MASK, MAX22200_FREQ_CFG3_SHIFT, MAX22200_CFG_CH_3, false})
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#define MAX22200_HSNLS3_MASK 0x00000040
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#define MAX22200_HSNLS3_SHIFT 6
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#define MAX22200_HSNLS3_FIELD ((RegisterField) {MAX22200_HSNLS3_MASK, MAX22200_HSNLS3_SHIFT, MAX22200_CFG_CH_3, false})
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#define MAX22200_VDRNCDR3_MASK 0x00000080
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#define MAX22200_VDRNCDR3_SHIFT 7
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#define MAX22200_VDRNCDR3_FIELD ((RegisterField) {MAX22200_VDRNCDR3_MASK, MAX22200_VDRNCDR3_SHIFT, MAX22200_CFG_CH_3, false})
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#define MAX22200_HIT_T3_MASK 0x0000FF00
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#define MAX22200_HIT_T3_SHIFT 8
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#define MAX22200_HIT_T3_FIELD ((RegisterField) {MAX22200_HIT_T3_MASK, MAX22200_HIT_T3_SHIFT, MAX22200_CFG_CH_3, false})
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#define MAX22200_HIT3_MASK 0x007F0000
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#define MAX22200_HIT3_SHIFT 16
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#define MAX22200_HIT3_FIELD ((RegisterField) {MAX22200_HIT3_MASK, MAX22200_HIT3_SHIFT, MAX22200_CFG_CH_3, false})
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#define MAX22200_TRGNSPI3_MASK 0x00800000
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#define MAX22200_TRGNSPI3_SHIFT 23
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#define MAX22200_TRGNSPI3_FIELD ((RegisterField) {MAX22200_TRGNSPI3_MASK, MAX22200_TRGNSPI3_SHIFT, MAX22200_CFG_CH_3, false})
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#define MAX22200_HOLD3_MASK 0x7F000000
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#define MAX22200_HOLD3_SHIFT 24
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#define MAX22200_HOLD3_FIELD ((RegisterField) {MAX22200_HOLD3_MASK, MAX22200_HOLD3_SHIFT, MAX22200_CFG_CH_3, false})
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#define MAX22200_HFS3_MASK 0x80000000
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#define MAX22200_HFS3_SHIFT 31
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#define MAX22200_HFS3_FIELD ((RegisterField) {MAX22200_HFS3_MASK, MAX22200_HFS3_SHIFT, MAX22200_CFG_CH_3, false})
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#define MAX22200_HHF_EN4_MASK 0x00000001
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#define MAX22200_HHF_EN4_SHIFT 0
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#define MAX22200_HHF_EN4_FIELD ((RegisterField) {MAX22200_HHF_EN4_MASK, MAX22200_HHF_EN4_SHIFT, MAX22200_CFG_CH_4, false})
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#define MAX22200_DPM_EN4_MASK 0x00000002
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#define MAX22200_DPM_EN4_SHIFT 1
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#define MAX22200_DPM_EN4_FIELD ((RegisterField) {MAX22200_DPM_EN4_MASK, MAX22200_DPM_EN4_SHIFT, MAX22200_CFG_CH_4, false})
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#define MAX22200_OL_EN4_MASK 0x00000004
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#define MAX22200_OL_EN4_SHIFT 2
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#define MAX22200_OL_EN4_FIELD ((RegisterField) {MAX22200_OL_EN4_MASK, MAX22200_OL_EN4_SHIFT, MAX22200_CFG_CH_4, false})
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#define MAX22200_SRC4_MASK 0x00000008
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#define MAX22200_SRC4_SHIFT 3
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#define MAX22200_SRC4_FIELD ((RegisterField) {MAX22200_SRC4_MASK, MAX22200_SRC4_SHIFT, MAX22200_CFG_CH_4, false})
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#define MAX22200_FREQ_CFG4_MASK 0x00000030
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#define MAX22200_FREQ_CFG4_SHIFT 4
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#define MAX22200_FREQ_CFG4_FIELD ((RegisterField) {MAX22200_FREQ_CFG4_MASK, MAX22200_FREQ_CFG4_SHIFT, MAX22200_CFG_CH_4, false})
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#define MAX22200_HSNLS4_MASK 0x00000040
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#define MAX22200_HSNLS4_SHIFT 6
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#define MAX22200_HSNLS4_FIELD ((RegisterField) {MAX22200_HSNLS4_MASK, MAX22200_HSNLS4_SHIFT, MAX22200_CFG_CH_4, false})
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#define MAX22200_VDRNCDR4_MASK 0x00000080
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#define MAX22200_VDRNCDR4_SHIFT 7
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#define MAX22200_VDRNCDR4_FIELD ((RegisterField) {MAX22200_VDRNCDR4_MASK, MAX22200_VDRNCDR4_SHIFT, MAX22200_CFG_CH_4, false})
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#define MAX22200_HIT_T4_MASK 0x0000FF00
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#define MAX22200_HIT_T4_SHIFT 8
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#define MAX22200_HIT_T4_FIELD ((RegisterField) {MAX22200_HIT_T4_MASK, MAX22200_HIT_T4_SHIFT, MAX22200_CFG_CH_4, false})
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#define MAX22200_HIT4_MASK 0x007F0000
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#define MAX22200_HIT4_SHIFT 16
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#define MAX22200_HIT4_FIELD ((RegisterField) {MAX22200_HIT4_MASK, MAX22200_HIT4_SHIFT, MAX22200_CFG_CH_4, false})
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#define MAX22200_TRGNSPI4_MASK 0x00800000
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#define MAX22200_TRGNSPI4_SHIFT 23
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#define MAX22200_TRGNSPI4_FIELD ((RegisterField) {MAX22200_TRGNSPI4_MASK, MAX22200_TRGNSPI4_SHIFT, MAX22200_CFG_CH_4, false})
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#define MAX22200_HOLD4_MASK 0x7F000000
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#define MAX22200_HOLD4_SHIFT 24
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#define MAX22200_HOLD4_FIELD ((RegisterField) {MAX22200_HOLD4_MASK, MAX22200_HOLD4_SHIFT, MAX22200_CFG_CH_4, false})
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#define MAX22200_HFS4_MASK 0x80000000
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#define MAX22200_HFS4_SHIFT 31
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#define MAX22200_HFS4_FIELD ((RegisterField) {MAX22200_HFS4_MASK, MAX22200_HFS4_SHIFT, MAX22200_CFG_CH_4, false})
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#define MAX22200_HHF_EN5_MASK 0x00000001
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#define MAX22200_HHF_EN5_SHIFT 0
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#define MAX22200_HHF_EN5_FIELD ((RegisterField) {MAX22200_HHF_EN5_MASK, MAX22200_HHF_EN5_SHIFT, MAX22200_CFG_CH_5, false})
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#define MAX22200_DPM_EN5_MASK 0x00000002
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#define MAX22200_DPM_EN5_SHIFT 1
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#define MAX22200_DPM_EN5_FIELD ((RegisterField) {MAX22200_DPM_EN5_MASK, MAX22200_DPM_EN5_SHIFT, MAX22200_CFG_CH_5, false})
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#define MAX22200_OL_EN5_MASK 0x00000004
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#define MAX22200_OL_EN5_SHIFT 2
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#define MAX22200_OL_EN5_FIELD ((RegisterField) {MAX22200_OL_EN5_MASK, MAX22200_OL_EN5_SHIFT, MAX22200_CFG_CH_5, false})
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#define MAX22200_SRC5_MASK 0x00000008
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#define MAX22200_SRC5_SHIFT 3
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#define MAX22200_SRC5_FIELD ((RegisterField) {MAX22200_SRC5_MASK, MAX22200_SRC5_SHIFT, MAX22200_CFG_CH_5, false})
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#define MAX22200_FREQ_CFG5_MASK 0x00000030
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#define MAX22200_FREQ_CFG5_SHIFT 4
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#define MAX22200_FREQ_CFG5_FIELD ((RegisterField) {MAX22200_FREQ_CFG5_MASK, MAX22200_FREQ_CFG5_SHIFT, MAX22200_CFG_CH_5, false})
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#define MAX22200_HSNLS5_MASK 0x00000040
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#define MAX22200_HSNLS5_SHIFT 6
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#define MAX22200_HSNLS5_FIELD ((RegisterField) {MAX22200_HSNLS5_MASK, MAX22200_HSNLS5_SHIFT, MAX22200_CFG_CH_5, false})
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#define MAX22200_VDRNCDR5_MASK 0x00000080
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#define MAX22200_VDRNCDR5_SHIFT 7
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#define MAX22200_VDRNCDR5_FIELD ((RegisterField) {MAX22200_VDRNCDR5_MASK, MAX22200_VDRNCDR5_SHIFT, MAX22200_CFG_CH_5, false})
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#define MAX22200_HIT_T5_MASK 0x0000FF00
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#define MAX22200_HIT_T5_SHIFT 8
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#define MAX22200_HIT_T5_FIELD ((RegisterField) {MAX22200_HIT_T5_MASK, MAX22200_HIT_T5_SHIFT, MAX22200_CFG_CH_5, false})
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#define MAX22200_HIT5_MASK 0x007F0000
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#define MAX22200_HIT5_SHIFT 16
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#define MAX22200_HIT5_FIELD ((RegisterField) {MAX22200_HIT5_MASK, MAX22200_HIT5_SHIFT, MAX22200_CFG_CH_5, false})
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#define MAX22200_TRGNSPI5_MASK 0x00800000
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#define MAX22200_TRGNSPI5_SHIFT 23
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#define MAX22200_TRGNSPI5_FIELD ((RegisterField) {MAX22200_TRGNSPI5_MASK, MAX22200_TRGNSPI5_SHIFT, MAX22200_CFG_CH_5, false})
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#define MAX22200_HOLD5_MASK 0x7F000000
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#define MAX22200_HOLD5_SHIFT 24
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#define MAX22200_HOLD5_FIELD ((RegisterField) {MAX22200_HOLD5_MASK, MAX22200_HOLD5_SHIFT, MAX22200_CFG_CH_5, false})
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#define MAX22200_HFS5_MASK 0x80000000
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#define MAX22200_HFS5_SHIFT 31
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#define MAX22200_HFS5_FIELD ((RegisterField) {MAX22200_HFS5_MASK, MAX22200_HFS5_SHIFT, MAX22200_CFG_CH_5, false})
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#define MAX22200_HHF_EN6_MASK 0x00000001
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#define MAX22200_HHF_EN6_SHIFT 0
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#define MAX22200_HHF_EN6_FIELD ((RegisterField) {MAX22200_HHF_EN6_MASK, MAX22200_HHF_EN6_SHIFT, MAX22200_CFG_CH_6, false})
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#define MAX22200_DPM_EN6_MASK 0x00000002
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#define MAX22200_DPM_EN6_SHIFT 1
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#define MAX22200_DPM_EN6_FIELD ((RegisterField) {MAX22200_DPM_EN6_MASK, MAX22200_DPM_EN6_SHIFT, MAX22200_CFG_CH_6, false})
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#define MAX22200_OL_EN6_MASK 0x00000004
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#define MAX22200_OL_EN6_SHIFT 2
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#define MAX22200_OL_EN6_FIELD ((RegisterField) {MAX22200_OL_EN6_MASK, MAX22200_OL_EN6_SHIFT, MAX22200_CFG_CH_6, false})
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#define MAX22200_SRC6_MASK 0x00000008
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#define MAX22200_SRC6_SHIFT 3
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#define MAX22200_SRC6_FIELD ((RegisterField) {MAX22200_SRC6_MASK, MAX22200_SRC6_SHIFT, MAX22200_CFG_CH_6, false})
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#define MAX22200_FREQ_CFG6_MASK 0x00000030
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#define MAX22200_FREQ_CFG6_SHIFT 4
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#define MAX22200_FREQ_CFG6_FIELD ((RegisterField) {MAX22200_FREQ_CFG6_MASK, MAX22200_FREQ_CFG6_SHIFT, MAX22200_CFG_CH_6, false})
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#define MAX22200_HSNLS6_MASK 0x00000040
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#define MAX22200_HSNLS6_SHIFT 6
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#define MAX22200_HSNLS6_FIELD ((RegisterField) {MAX22200_HSNLS6_MASK, MAX22200_HSNLS6_SHIFT, MAX22200_CFG_CH_6, false})
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#define MAX22200_VDRNCDR6_MASK 0x00000080
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#define MAX22200_VDRNCDR6_SHIFT 7
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#define MAX22200_VDRNCDR6_FIELD ((RegisterField) {MAX22200_VDRNCDR6_MASK, MAX22200_VDRNCDR6_SHIFT, MAX22200_CFG_CH_6, false})
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#define MAX22200_HIT_T6_MASK 0x0000FF00
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#define MAX22200_HIT_T6_SHIFT 8
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#define MAX22200_HIT_T6_FIELD ((RegisterField) {MAX22200_HIT_T6_MASK, MAX22200_HIT_T6_SHIFT, MAX22200_CFG_CH_6, false})
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#define MAX22200_HIT6_MASK 0x007F0000
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#define MAX22200_HIT6_SHIFT 16
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#define MAX22200_HIT6_FIELD ((RegisterField) {MAX22200_HIT6_MASK, MAX22200_HIT6_SHIFT, MAX22200_CFG_CH_6, false})
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#define MAX22200_TRGNSPI6_MASK 0x00800000
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#define MAX22200_TRGNSPI6_SHIFT 23
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#define MAX22200_TRGNSPI6_FIELD ((RegisterField) {MAX22200_TRGNSPI6_MASK, MAX22200_TRGNSPI6_SHIFT, MAX22200_CFG_CH_6, false})
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#define MAX22200_HOLD6_MASK 0x7F000000
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#define MAX22200_HOLD6_SHIFT 24
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#define MAX22200_HOLD6_FIELD ((RegisterField) {MAX22200_HOLD6_MASK, MAX22200_HOLD6_SHIFT, MAX22200_CFG_CH_6, false})
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#define MAX22200_HFS6_MASK 0x80000000
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#define MAX22200_HFS6_SHIFT 31
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#define MAX22200_HFS6_FIELD ((RegisterField) {MAX22200_HFS6_MASK, MAX22200_HFS6_SHIFT, MAX22200_CFG_CH_6, false})
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#define MAX22200_HHF_EN7_MASK 0x00000001
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#define MAX22200_HHF_EN7_SHIFT 0
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#define MAX22200_HHF_EN7_FIELD ((RegisterField) {MAX22200_HHF_EN7_MASK, MAX22200_HHF_EN7_SHIFT, MAX22200_CFG_CH_7, false})
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#define MAX22200_DPM_EN7_MASK 0x00000002
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#define MAX22200_DPM_EN7_SHIFT 1
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#define MAX22200_DPM_EN7_FIELD ((RegisterField) {MAX22200_DPM_EN7_MASK, MAX22200_DPM_EN7_SHIFT, MAX22200_CFG_CH_7, false})
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#define MAX22200_OL_EN7_MASK 0x00000004
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#define MAX22200_OL_EN7_SHIFT 2
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#define MAX22200_OL_EN7_FIELD ((RegisterField) {MAX22200_OL_EN7_MASK, MAX22200_OL_EN7_SHIFT, MAX22200_CFG_CH_7, false})
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#define MAX22200_SRC7_MASK 0x00000008
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#define MAX22200_SRC7_SHIFT 3
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#define MAX22200_SRC7_FIELD ((RegisterField) {MAX22200_SRC7_MASK, MAX22200_SRC7_SHIFT, MAX22200_CFG_CH_7, false})
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#define MAX22200_FREQ_CFG7_MASK 0x00000030
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#define MAX22200_FREQ_CFG7_SHIFT 4
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#define MAX22200_FREQ_CFG7_FIELD ((RegisterField) {MAX22200_FREQ_CFG7_MASK, MAX22200_FREQ_CFG7_SHIFT, MAX22200_CFG_CH_7, false})
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#define MAX22200_HSNLS7_MASK 0x00000040
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#define MAX22200_HSNLS7_SHIFT 6
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#define MAX22200_HSNLS7_FIELD ((RegisterField) {MAX22200_HSNLS7_MASK, MAX22200_HSNLS7_SHIFT, MAX22200_CFG_CH_7, false})
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#define MAX22200_VDRNCDR7_MASK 0x00000080
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#define MAX22200_VDRNCDR7_SHIFT 7
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#define MAX22200_VDRNCDR7_FIELD ((RegisterField) {MAX22200_VDRNCDR7_MASK, MAX22200_VDRNCDR7_SHIFT, MAX22200_CFG_CH_7, false})
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#define MAX22200_HIT_T7_MASK 0x0000FF00
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#define MAX22200_HIT_T7_SHIFT 8
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#define MAX22200_HIT_T7_FIELD ((RegisterField) {MAX22200_HIT_T7_MASK, MAX22200_HIT_T7_SHIFT, MAX22200_CFG_CH_7, false})
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#define MAX22200_HIT7_MASK 0x007F0000
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#define MAX22200_HIT7_SHIFT 16
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#define MAX22200_HIT7_FIELD ((RegisterField) {MAX22200_HIT7_MASK, MAX22200_HIT7_SHIFT, MAX22200_CFG_CH_7, false})
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#define MAX22200_TRGNSPI7_MASK 0x00800000
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#define MAX22200_TRGNSPI7_SHIFT 23
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#define MAX22200_TRGNSPI7_FIELD ((RegisterField) {MAX22200_TRGNSPI7_MASK, MAX22200_TRGNSPI7_SHIFT, MAX22200_CFG_CH_7, false})
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#define MAX22200_HOLD7_MASK 0x7F000000
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#define MAX22200_HOLD7_SHIFT 24
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#define MAX22200_HOLD7_FIELD ((RegisterField) {MAX22200_HOLD7_MASK, MAX22200_HOLD7_SHIFT, MAX22200_CFG_CH_7, false})
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#define MAX22200_HFS7_MASK 0x80000000
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#define MAX22200_HFS7_SHIFT 31
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#define MAX22200_HFS7_FIELD ((RegisterField) {MAX22200_HFS7_MASK, MAX22200_HFS7_SHIFT, MAX22200_CFG_CH_7, false})
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//#define MAX22200_DPM_MASK 0x000000FF
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//#define MAX22200_DPM_SHIFT 0
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//#define MAX22200_DPM_FIELD ((RegisterField) {MAX22200_DPM_MASK, MAX22200_DPM_SHIFT, MAX22200_FAULT, false})
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//#define MAX22200_OLF_MASK 0x0000FF00
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//#define MAX22200_OLF_SHIFT 8
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//#define MAX22200_OLF_FIELD ((RegisterField) {MAX22200_OLF_MASK, MAX22200_OLF_SHIFT, MAX22200_FAULT, false})
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//#define MAX22200_HHF_MASK 0x00FF0000
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//#define MAX22200_HHF_SHIFT 16
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//#define MAX22200_HHF_FIELD ((RegisterField) {MAX22200_HHF_MASK, MAX22200_HHF_SHIFT, MAX22200_FAULT, false})
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//#define MAX22200_OCP_MASK 0xFF000000
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//#define MAX22200_OCP_SHIFT 24
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//#define MAX22200_OCP_FIELD ((RegisterField) {MAX22200_OCP_MASK, MAX22200_OCP_SHIFT, MAX22200_FAULT, false})
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#define MAX22200_DPM_CFG0_IPTH_MASK 0x0000000F
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#define MAX22200_DPM_CFG0_IPTH_SHIFT 0
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#define MAX22200_DPM_CFG0_IPTH_FIELD ((RegisterField) {MAX22200_DPM_CFG0_IPTH_MASK, MAX22200_DPM_CFG0_IPTH_SHIFT, MAX22200_CFG_DPM, false})
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#define MAX22200_DPM_CFG0_T_MASK 0x000000F0
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#define MAX22200_DPM_CFG0_T_SHIFT 4
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#define MAX22200_DPM_CFG0_T_FIELD ((RegisterField) {MAX22200_DPM_CFG0_T_MASK, MAX22200_DPM_CFG0_T_SHIFT, MAX22200_CFG_DPM, false})
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#define MAX22200_DPM_CFG1_ISTART_MASK 0x00007F00
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#define MAX22200_DPM_CFG1_ISTART_SHIFT 8
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#define MAX22200_DPM_CFG1_ISTART_FIELD ((RegisterField) {MAX22200_DPM_CFG1_ISTART_MASK, MAX22200_DPM_CFG1_ISTART_SHIFT, MAX22200_CFG_DPM, false})
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//#define MAX22200_8BITN32BITS_MASK 0x00000001
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//#define MAX22200_8BITN32BITS_SHIFT 0
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//#define MAX22200_8BITN32BITS_FIELD ((RegisterField) {MAX22200_8BITN32BITS_MASK, MAX22200_8BITN32BITS_SHIFT, MAX22200_CMDREG, false})
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//#define MAX22200_A_BNK_MASK 0x0000007E
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//#define MAX22200_A_BNK_SHIFT 1
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//#define MAX22200_A_BNK_FIELD ((RegisterField) {MAX22200_A_BNK_MASK, MAX22200_A_BNK_SHIFT, MAX22200_CMDREG, false})
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//#define MAX22200_RBW_MASK 0x00000080
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//#define MAX22200_RBW_SHIFT 1
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//#define MAX22200_RBW_FIELD ((RegisterField) {MAX22200_RBW_MASK, MAX22200_RBW_SHIFT, MAX22200_CMDREG, false})
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#endif
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