876 lines
64 KiB
C
Executable File
876 lines
64 KiB
C
Executable File
/*******************************************************************************
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* Copyright © 2024 Analog Devices Inc. All Rights Reserved.
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* This software is proprietary to Analog Devices, Inc. and its licensors.
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*******************************************************************************/
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#ifndef TMC5241_HW_ABSTRACTION
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#define TMC5241_HW_ABSTRACTION
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//constants
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#define TMC5241_REGISTER_COUNT 128
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#define TMC5241_MOTORS 1
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#define TMC5241_WRITE_BIT 0x80
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#define TMC5241_ADDRESS_MASK 0x7F
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#define TMC5241_MAX_VELOCITY 8388096
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#define TMC5241_MAX_ACCELERATION u16_MAX
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#define DEFAULT_ICID 0
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// ramp modes (Register TMC5241_RAMPMODE)
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#define TMC5241_MODE_POSITION 0
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#define TMC5241_MODE_VELPOS 1
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#define TMC5241_MODE_VELNEG 2
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#define TMC5241_MODE_HOLD 3
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// limit switch mode bits (Register TMC5241_SWMODE)
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#define TMC5241_SW_STOPL_ENABLE 0x0001
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#define TMC5241_SW_STOPR_ENABLE 0x0002
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#define TMC5241_SW_STOPL_POLARITY 0x0004
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#define TMC5241_SW_STOPR_POLARITY 0x0008
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#define TMC5241_SW_SWAP_LR 0x0010
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#define TMC5241_SW_LATCH_L_ACT 0x0020
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#define TMC5241_SW_LATCH_L_INACT 0x0040
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#define TMC5241_SW_LATCH_R_ACT 0x0080
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#define TMC5241_SW_LATCH_R_INACT 0x0100
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#define TMC5241_SW_LATCH_ENC 0x0200
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#define TMC5241_SW_SG_STOP 0x0400
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#define TMC5241_SW_SOFTSTOP 0x0800
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// Status bits (Register TMC5241_RAMPSTAT)
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#define TMC5241_RS_STOPL 0x0001
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#define TMC5241_RS_STOPR 0x0002
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#define TMC5241_RS_LATCHL 0x0004
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#define TMC5241_RS_LATCHR 0x0008
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#define TMC5241_RS_EV_STOPL 0x0010
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#define TMC5241_RS_EV_STOPR 0x0020
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#define TMC5241_RS_EV_STOP_SG 0x0040
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#define TMC5241_RS_EV_POSREACHED 0x0080
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#define TMC5241_RS_VELREACHED 0x0100
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#define TMC5241_RS_POSREACHED 0x0200
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#define TMC5241_RS_VZERO 0x0400
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#define TMC5241_RS_ZEROWAIT 0x0800
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#define TMC5241_RS_SECONDMOVE 0x1000
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#define TMC5241_RS_SG 0x2000
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// Encoderbits (Register TMC5241_ENCMODE)
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#define TMC5241_EM_DECIMAL 0x0400
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#define TMC5241_EM_LATCH_XACT 0x0200
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#define TMC5241_EM_CLR_XENC 0x0100
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#define TMC5241_EM_NEG_EDGE 0x0080
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#define TMC5241_EM_POS_EDGE 0x0040
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#define TMC5241_EM_CLR_ONCE 0x0020
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#define TMC5241_EM_CLR_CONT 0x0010
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#define TMC5241_EM_IGNORE_AB 0x0008
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#define TMC5241_EM_POL_N 0x0004
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#define TMC5241_EM_POL_B 0x0002
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#define TMC5241_EM_POL_A 0x0001
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// Registers in TMC5241
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#define TMC5241_GCONF 0x00
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#define TMC5241_GSTAT 0x01
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#define TMC5241_IFCNT 0x02
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#define TMC5241_SLAVECONF 0x03
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#define TMC5241_IOIN 0x04
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#define TMC5241_X_COMPARE 0x05
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#define TMC5241_X_COMPARE_REPEAT 0x06
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#define TMC5241_DIAG_GCONF 0x07
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#define TMC5241_DRV_CONF 0x0A
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#define TMC5241_GLOBAL_SCALER 0x0B
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#define TMC5241_IHOLD_IRUN 0x10
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#define TMC5241_TPOWERDOWN 0x11
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#define TMC5241_TSTEP 0x12
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#define TMC5241_TPWMTHRS 0x13
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#define TMC5241_TCOOLTHRS 0x14
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#define TMC5241_THIGH 0x15
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#define TMC5241_RAMPMODE 0x20
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#define TMC5241_XACTUAL 0x21
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#define TMC5241_VACTUAL 0x22
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#define TMC5241_VSTART 0x23
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#define TMC5241_A1 0x24
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#define TMC5241_V1 0x25
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#define TMC5241_AMAX 0x26
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#define TMC5241_VMAX 0x27
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#define TMC5241_DMAX 0x28
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#define TMC5241_TVMAX 0x29
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#define TMC5241_D1 0x2A
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#define TMC5241_VSTOP 0x2B
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#define TMC5241_TZEROWAIT 0x2C
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#define TMC5241_XTARGET 0x2D
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#define TMC5241_V2 0x2E
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#define TMC5241_A2 0x2F
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#define TMC5241_D2 0x30
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#define TMC5241_AACTUAL 0x31
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#define TMC5241_VDCMIN 0x33
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#define TMC5241_SW_MODE 0x34
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#define TMC5241_RAMP_STAT 0x35
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#define TMC5241_XLATCH 0x36
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#define TMC5241_ENCMODE 0x38
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#define TMC5241_X_ENC 0x39
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#define TMC5241_ENC_CONST 0x3A
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#define TMC5241_ENC_STATUS 0x3B
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#define TMC5241_ENC_LATCH 0x3C
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#define TMC5241_ENC_DEVIATION 0x3D
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#define TMC5241_VIRTUAL_STOP_L 0x3E
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#define TMC5241_VIRTUAL_STOP_R 0x3F
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#define TMC5241_ADC_VSUPPLY_AIN 0x50
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#define TMC5241_ADC_TEMP 0x51
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#define TMC5241_OTW_OV_VTH 0x52
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#define TMC5241_MSLUT__ 0x60
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//#define TMC5241_MSLUT__ 0x61
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//#define TMC5241_MSLUT__ 0x62
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//#define TMC5241_MSLUT__ 0x63
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//#define TMC5241_MSLUT__ 0x64
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//#define TMC5241_MSLUT__ 0x65
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//#define TMC5241_MSLUT__ 0x66
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//#define TMC5241_MSLUT__ 0x67
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#define TMC5241_MSLUTSEL 0x68
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#define TMC5241_MSLUTSTART 0x69
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#define TMC5241_MSCNT 0x6A
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#define TMC5241_MSCURACT 0x6B
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#define TMC5241_CHOPCONF 0x6C
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#define TMC5241_COOLCONF 0x6D
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#define TMC5241_DCCTRL 0x6E
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#define TMC5241_DRV_STATUS 0x6F
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#define TMC5241_PWMCONF 0x70
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#define TMC5241_PWM_SCALE 0x71
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#define TMC5241_PWM_AUTO 0x72
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#define TMC5241_SG4_THRS 0x74
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#define TMC5241_SG4_RESULT 0x75
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#define TMC5241_SG4_IND 0x76
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// Register fields in TMC5241
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// Status fields returned with every SPI transaction
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#define TMC5241_SPI_STATUS_RESET_FLAG_MASK 0x01 /* GSTAT[0] - 1: Signals, that a reset has occurred (clear by reading GSTAT) */
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#define TMC5241_SPI_STATUS_RESET_FLAG_SHIFT 0
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#define TMC5241_SPI_STATUS_RESET_FLAG_FIELD ((RegisterField) { TMC5241_SPI_STATUS_RESET_FLAG_MASK, TMC5241_SPI_STATUS_RESET_FLAG_SHIFT, TMC5241_GSTAT, false })
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#define TMC5241_SPI_STATUS_DRIVER_ERROR_MASK 0x02 /* GSTAT[1] – 1: Signals driver 1 driver error (clear by reading GSTAT) */
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#define TMC5241_SPI_STATUS_DRIVER_ERROR_SHIFT 1
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#define TMC5241_SPI_STATUS_DRIVER_ERROR_FIELD ((RegisterField) { TMC5241_SPI_STATUS_DRIVER_ERROR_MASK, TMC5241_SPI_STATUS_DRIVER_ERROR_SHIFT, TMC5241_GSTAT, false })
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#define TMC5241_SPI_STATUS_SG2_MASK 0x04 /* DRV_STATUS[24] – 1: Signals StallGuard flag active */
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#define TMC5241_SPI_STATUS_SG2_SHIFT 2
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#define TMC5241_SPI_STATUS_SG2_FIELD ((RegisterField) { TMC5241_SPI_STATUS_SG2_MASK, TMC5241_SPI_STATUS_SG2_SHIFT, TMC5241_DRVSTATUS, false })
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#define TMC5241_SPI_STATUS_STANDSTILL_MASK 0x08 /* DRV_STATUS[31] – 1: Signals motor stand still */
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#define TMC5241_SPI_STATUS_STANDSTILL_SHIFT 3
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#define TMC5241_SPI_STATUS_STANDSTILL_FIELD ((RegisterField) { TMC5241_SPI_STATUS_STANDSTILL_MASK, TMC5241_SPI_STATUS_STANDSTILL_SHIFT, TMC5241_DRVSTATUS, false })
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#define TMC5241_SPI_STATUS_VELOCITY_REACHED_MASK 0x10 /* RAMP_STAT[8] – 1: Signals target velocity reached (motion controller only) */
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#define TMC5241_SPI_STATUS_VELOCITY_REACHED_SHIFT 4
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#define TMC5241_SPI_STATUS_VELOCITY_REACHED_FIELD ((RegisterField) { TMC5241_SPI_STATUS_VELOCITY_REACHED_MASK, TMC5241_SPI_STATUS_VELOCITY_REACHED_SHIFT, TMC5241_RAMPSTAT, false })
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#define TMC5241_SPI_STATUS_POSITION_REACHED_MASK 0x20 /* RAMP_STAT[9] – 1: Signals target position reached (motion controller only) */
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#define TMC5241_SPI_STATUS_POSITION_REACHED_SHIFT 5
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#define TMC5241_SPI_STATUS_POSITION_REACHED_FIELD ((RegisterField) { TMC5241_SPI_STATUS_POSITION_REACHED_MASK, TMC5241_SPI_STATUS_POSITION_REACHED_SHIFT, TMC5241_RAMPSTAT, false })
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#define TMC5241_SPI_STATUS_STATUS_STOP_L_MASK 0x40 /* RAMP_STAT[0] – 1: Signals stop left switch status (motion controller only) */
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#define TMC5241_SPI_STATUS_STATUS_STOP_L_SHIFT 6
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#define TMC5241_SPI_STATUS_STATUS_STOP_L_FIELD ((RegisterField) { TMC5241_SPI_STATUS_STATUS_STOP_L_MASK, TMC5241_SPI_STATUS_STATUS_STOP_L_SHIFT, TMC5241_RAMPSTAT, false })
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#define TMC5241_SPI_STATUS_STATUS_STOP_R_MASK 0x80 /* RAMP_STAT[1] – 1: Signals stop right switch status (motion controller only) */
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#define TMC5241_SPI_STATUS_STATUS_STOP_R_SHIFT 7
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#define TMC5241_SPI_STATUS_STATUS_STOP_R_FIELD ((RegisterField) { TMC5241_SPI_STATUS_STATUS_STOP_R_MASK, TMC5241_SPI_STATUS_STATUS_STOP_R_SHIFT, TMC5241_RAMPSTAT, false })
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// Configuration & status registers
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#define TMC5241_FAST_STANDSTILL_MASK 0x00000002
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#define TMC5241_FAST_STANDSTILL_SHIFT 1
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#define TMC5241_FAST_STANDSTILL_FIELD ((RegisterField) {TMC5241_FAST_STANDSTILL_MASK, TMC5241_FAST_STANDSTILL_SHIFT, TMC5241_GCONF, false})
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#define TMC5241_EN_PWM_MODE_MASK 0x00000004
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#define TMC5241_EN_PWM_MODE_SHIFT 2
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#define TMC5241_EN_PWM_MODE_FIELD ((RegisterField) {TMC5241_EN_PWM_MODE_MASK, TMC5241_EN_PWM_MODE_SHIFT, TMC5241_GCONF, false})
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#define TMC5241_MULTISTEP_FILT_MASK 0x00000008
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#define TMC5241_MULTISTEP_FILT_SHIFT 3
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#define TMC5241_MULTISTEP_FILT_FIELD ((RegisterField) {TMC5241_MULTISTEP_FILT_MASK, TMC5241_MULTISTEP_FILT_SHIFT, TMC5241_GCONF, false})
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#define TMC5241_SHAFT_MASK 0x00000010
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#define TMC5241_SHAFT_SHIFT 4
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#define TMC5241_SHAFT_FIELD ((RegisterField) {TMC5241_SHAFT_MASK, TMC5241_SHAFT_SHIFT, TMC5241_GCONF, false})
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#define TMC5241_DIAG0_NINT_STEP_MASK 0x00000080
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#define TMC5241_DIAG0_NINT_STEP_SHIFT 7
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#define TMC5241_DIAG0_NINT_STEP_FIELD ((RegisterField) {TMC5241_DIAG0_NINT_STEP_MASK, TMC5241_DIAG0_NINT_STEP_SHIFT, TMC5241_GCONF, false})
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#define TMC5241_DIAG1_NPOSCOMP_DIR_MASK 0x00000100
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#define TMC5241_DIAG1_NPOSCOMP_DIR_SHIFT 8
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#define TMC5241_DIAG1_NPOSCOMP_DIR_FIELD ((RegisterField) {TMC5241_DIAG1_NPOSCOMP_DIR_MASK, TMC5241_DIAG1_NPOSCOMP_DIR_SHIFT, TMC5241_GCONF, false})
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#define TMC5241_DIAG0_INT_PUSHPULL_MASK 0x00001000
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#define TMC5241_DIAG0_INT_PUSHPULL_SHIFT 12
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#define TMC5241_DIAG0_INT_PUSHPULL_FIELD ((RegisterField) {TMC5241_DIAG0_INT_PUSHPULL_MASK, TMC5241_DIAG0_INT_PUSHPULL_SHIFT, TMC5241_GCONF, false})
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#define TMC5241_DIAG1_POSCOMP_PUSHPULL_MASK 0x00002000
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#define TMC5241_DIAG1_POSCOMP_PUSHPULL_SHIFT 13
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#define TMC5241_DIAG1_POSCOMP_PUSHPULL_FIELD ((RegisterField) {TMC5241_DIAG1_POSCOMP_PUSHPULL_MASK, TMC5241_DIAG1_POSCOMP_PUSHPULL_SHIFT, TMC5241_GCONF, false})
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#define TMC5241_SMALL_HYSTERESIS_MASK 0x00004000
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#define TMC5241_SMALL_HYSTERESIS_SHIFT 14
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#define TMC5241_SMALL_HYSTERESIS_FIELD ((RegisterField) {TMC5241_SMALL_HYSTERESIS_MASK, TMC5241_SMALL_HYSTERESIS_SHIFT, TMC5241_GCONF, false})
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#define TMC5241_STOP_ENABLE_MASK 0x00008000
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#define TMC5241_STOP_ENABLE_SHIFT 15
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#define TMC5241_STOP_ENABLE_FIELD ((RegisterField) {TMC5241_STOP_ENABLE_MASK, TMC5241_STOP_ENABLE_SHIFT, TMC5241_GCONF, false})
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#define TMC5241_DIRECT_MODE_MASK 0x00010000
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#define TMC5241_DIRECT_MODE_SHIFT 16
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#define TMC5241_DIRECT_MODE_FIELD ((RegisterField) {TMC5241_DIRECT_MODE_MASK, TMC5241_DIRECT_MODE_SHIFT, TMC5241_GCONF, false})
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#define TMC5241_LENGTH_STEP_PULSE_MASK 0x001E0000
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#define TMC5241_LENGTH_STEP_PULSE_SHIFT 17
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#define TMC5241_LENGTH_STEP_PULSE_FIELD ((RegisterField) {TMC5241_LENGTH_STEP_PULSE_MASK, TMC5241_LENGTH_STEP_PULSE_SHIFT, TMC5241_GCONF, false})
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#define TMC5241_RESET_MASK 0x00000001
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#define TMC5241_RESET_SHIFT 0
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#define TMC5241_RESET_FIELD ((RegisterField) {TMC5241_RESET_MASK, TMC5241_RESET_SHIFT, TMC5241_GSTAT, false})
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#define TMC5241_DRV_ERR_MASK 0x00000002
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#define TMC5241_DRV_ERR_SHIFT 1
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#define TMC5241_DRV_ERR_FIELD ((RegisterField) {TMC5241_DRV_ERR_MASK, TMC5241_DRV_ERR_SHIFT, TMC5241_GSTAT, false})
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#define TMC5241_UV_CP_MASK 0x00000004
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#define TMC5241_UV_CP_SHIFT 2
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#define TMC5241_UV_CP_FIELD ((RegisterField) {TMC5241_UV_CP_MASK, TMC5241_UV_CP_SHIFT, TMC5241_GSTAT, false})
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#define TMC5241_REGISTER_RESET_MASK 0x00000008
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#define TMC5241_REGISTER_RESET_SHIFT 3
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#define TMC5241_REGISTER_RESET_FIELD ((RegisterField) {TMC5241_REGISTER_RESET_MASK, TMC5241_REGISTER_RESET_SHIFT, TMC5241_GSTAT, false})
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#define TMC5241_VM_UVLO_MASK 0x00000010
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#define TMC5241_VM_UVLO_SHIFT 4
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#define TMC5241_VM_UVLO_FIELD ((RegisterField) {TMC5241_VM_UVLO_MASK, TMC5241_VM_UVLO_SHIFT, TMC5241_GSTAT, false})
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#define TMC5241_IFCNT_MASK 0x000000FF
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#define TMC5241_IFCNT_SHIFT 0
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#define TMC5241_IFCNT_FIELD ((RegisterField) {TMC5241_IFCNT_MASK, TMC5241_IFCNT_SHIFT, TMC5241_IFCNT, false})
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#define TMC5241_SLAVEADDR_MASK 0x000000FF
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#define TMC5241_SLAVEADDR_SHIFT 0
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#define TMC5241_SLAVEADDR_FIELD ((RegisterField) {TMC5241_SLAVEADDR_MASK, TMC5241_SLAVEADDR_SHIFT, TMC5241_SLAVECONF, false})
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#define TMC5241_SENDDELAY_MASK 0x00000F00
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#define TMC5241_SENDDELAY_SHIFT 8
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#define TMC5241_SENDDELAY_FIELD ((RegisterField) {TMC5241_SENDDELAY_MASK, TMC5241_SENDDELAY_SHIFT, TMC5241_SLAVECONF, false})
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#define TMC5241_REFL_MASK 0x00000001
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#define TMC5241_REFL_SHIFT 0
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#define TMC5241_REFL_FIELD ((RegisterField) {TMC5241_REFL_MASK, TMC5241_REFL_SHIFT, TMC5241_IOIN, false})
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#define TMC5241_REFR_MASK 0x00000002
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#define TMC5241_REFR_SHIFT 1
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#define TMC5241_REFR_FIELD ((RegisterField) {TMC5241_REFR_MASK, TMC5241_REFR_SHIFT, TMC5241_IOIN, false})
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#define TMC5241_ENCB_MASK 0x00000004
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#define TMC5241_ENCB_SHIFT 2
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#define TMC5241_ENCB_FIELD ((RegisterField) {TMC5241_ENCB_MASK, TMC5241_ENCB_SHIFT, TMC5241_IOIN, false})
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#define TMC5241_ENCA_MASK 0x00000008
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#define TMC5241_ENCA_SHIFT 3
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#define TMC5241_ENCA_FIELD ((RegisterField) {TMC5241_ENCA_MASK, TMC5241_ENCA_SHIFT, TMC5241_IOIN, false})
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#define TMC5241_DRV_ENN_MASK 0x00000010
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#define TMC5241_DRV_ENN_SHIFT 4
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#define TMC5241_DRV_ENN_FIELD ((RegisterField) {TMC5241_DRV_ENN_MASK, TMC5241_DRV_ENN_SHIFT, TMC5241_IOIN, false})
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#define TMC5241_ENCN_MASK 0x00000020
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#define TMC5241_ENCN_SHIFT 5
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#define TMC5241_ENCN_FIELD ((RegisterField) {TMC5241_ENCN_MASK, TMC5241_ENCN_SHIFT, TMC5241_IOIN, false})
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#define TMC5241_UART_EN_MASK 0x00000040
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#define TMC5241_UART_EN_SHIFT 6
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#define TMC5241_UART_EN_FIELD ((RegisterField) {TMC5241_UART_EN_MASK, TMC5241_UART_EN_SHIFT, TMC5241_IOIN, false})
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#define TMC5241_RESERVED_MASK 0x00000080
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#define TMC5241_RESERVED_SHIFT 7
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#define TMC5241_RESERVED_FIELD ((RegisterField) {TMC5241_RESERVED_MASK, TMC5241_RESERVED_SHIFT, TMC5241_IOIN, false})
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#define TMC5241_COMP_A_MASK 0x00000100
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#define TMC5241_COMP_A_SHIFT 8
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#define TMC5241_COMP_A_FIELD ((RegisterField) {TMC5241_COMP_A_MASK, TMC5241_COMP_A_SHIFT, TMC5241_IOIN, false})
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#define TMC5241_COMP_B_MASK 0x00000200
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#define TMC5241_COMP_B_SHIFT 9
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#define TMC5241_COMP_B_FIELD ((RegisterField) {TMC5241_COMP_B_MASK, TMC5241_COMP_B_SHIFT, TMC5241_IOIN, false})
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#define TMC5241_COMP_A1_A2_MASK 0x00000400
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#define TMC5241_COMP_A1_A2_SHIFT 10
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#define TMC5241_COMP_A1_A2_FIELD ((RegisterField) {TMC5241_COMP_A1_A2_MASK, TMC5241_COMP_A1_A2_SHIFT, TMC5241_IOIN, false})
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#define TMC5241_COMP_B1_B2_MASK 0x00000800
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#define TMC5241_COMP_B1_B2_SHIFT 11
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#define TMC5241_COMP_B1_B2_FIELD ((RegisterField) {TMC5241_COMP_B1_B2_MASK, TMC5241_COMP_B1_B2_SHIFT, TMC5241_IOIN, false})
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#define TMC5241_OUTPUT_MASK 0x00001000
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#define TMC5241_OUTPUT_SHIFT 12
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#define TMC5241_OUTPUT_FIELD ((RegisterField) {TMC5241_OUTPUT_MASK, TMC5241_OUTPUT_SHIFT, TMC5241_IOIN, false})
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#define TMC5241_EXT_RES_DET_MASK 0x00002000
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#define TMC5241_EXT_RES_DET_SHIFT 13
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#define TMC5241_EXT_RES_DET_FIELD ((RegisterField) {TMC5241_EXT_RES_DET_MASK, TMC5241_EXT_RES_DET_SHIFT, TMC5241_IOIN, false})
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#define TMC5241_EXT_CLK_MASK 0x00004000
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#define TMC5241_EXT_CLK_SHIFT 14
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#define TMC5241_EXT_CLK_FIELD ((RegisterField) {TMC5241_EXT_CLK_MASK, TMC5241_EXT_CLK_SHIFT, TMC5241_IOIN, false})
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#define TMC5241_ADC_ERR_MASK 0x00008000
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#define TMC5241_ADC_ERR_SHIFT 15
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#define TMC5241_ADC_ERR_FIELD ((RegisterField) {TMC5241_ADC_ERR_MASK, TMC5241_ADC_ERR_SHIFT, TMC5241_IOIN, false})
|
||
#define TMC5241_SILICON_RV_MASK 0x00070000
|
||
#define TMC5241_SILICON_RV_SHIFT 16
|
||
#define TMC5241_SILICON_RV_FIELD ((RegisterField) {TMC5241_SILICON_RV_MASK, TMC5241_SILICON_RV_SHIFT, TMC5241_IOIN, false})
|
||
#define TMC5241_VERSION_MASK 0xFF000000
|
||
#define TMC5241_VERSION_SHIFT 24
|
||
#define TMC5241_VERSION_FIELD ((RegisterField) {TMC5241_VERSION_MASK, TMC5241_VERSION_SHIFT, TMC5241_IOIN, false})
|
||
#define TMC5241_X_COMPARE_MASK 0xFFFFFFFF
|
||
#define TMC5241_X_COMPARE_SHIFT 0
|
||
#define TMC5241_X_COMPARE_FIELD ((RegisterField) {TMC5241_X_COMPARE_MASK, TMC5241_X_COMPARE_SHIFT, TMC5241_X_COMPARE, true})
|
||
#define TMC5241_X_COMPARE_REPEAT_MASK 0x00FFFFFF
|
||
#define TMC5241_X_COMPARE_REPEAT_SHIFT 0
|
||
#define TMC5241_X_COMPARE_REPEAT_FIELD ((RegisterField) {TMC5241_X_COMPARE_REPEAT_MASK, TMC5241_X_COMPARE_REPEAT_SHIFT, TMC5241_X_COMPARE_REPEAT, false})
|
||
#define TMC5241_DIAG0_ERROR_MASK 0x00000001
|
||
#define TMC5241_DIAG0_ERROR_SHIFT 0
|
||
#define TMC5241_DIAG0_ERROR_FIELD ((RegisterField) {TMC5241_DIAG0_ERROR_MASK, TMC5241_DIAG0_ERROR_SHIFT, TMC5241_DIAG_GCONF, false})
|
||
#define TMC5241_DIAG0_OTPW_MASK 0x00000002
|
||
#define TMC5241_DIAG0_OTPW_SHIFT 1
|
||
#define TMC5241_DIAG0_OTPW_FIELD ((RegisterField) {TMC5241_DIAG0_OTPW_MASK, TMC5241_DIAG0_OTPW_SHIFT, TMC5241_DIAG_GCONF, false})
|
||
#define TMC5241_DIAG0_STALL_MASK 0x00000004
|
||
#define TMC5241_DIAG0_STALL_SHIFT 2
|
||
#define TMC5241_DIAG0_STALL_FIELD ((RegisterField) {TMC5241_DIAG0_STALL_MASK, TMC5241_DIAG0_STALL_SHIFT, TMC5241_DIAG_GCONF, false})
|
||
#define TMC5241_DIAG0_INDEX_MASK 0x00000008
|
||
#define TMC5241_DIAG0_INDEX_SHIFT 3
|
||
#define TMC5241_DIAG0_INDEX_FIELD ((RegisterField) {TMC5241_DIAG0_INDEX_MASK, TMC5241_DIAG0_INDEX_SHIFT, TMC5241_DIAG_GCONF, false})
|
||
#define TMC5241_DIAG0_STEP_MASK 0x00000010
|
||
#define TMC5241_DIAG0_STEP_SHIFT 4
|
||
#define TMC5241_DIAG0_STEP_FIELD ((RegisterField) {TMC5241_DIAG0_STEP_MASK, TMC5241_DIAG0_STEP_SHIFT, TMC5241_DIAG_GCONF, false})
|
||
#define TMC5241_DIAG0_DIR_MASK 0x00000020
|
||
#define TMC5241_DIAG0_DIR_SHIFT 5
|
||
#define TMC5241_DIAG0_DIR_FIELD ((RegisterField) {TMC5241_DIAG0_DIR_MASK, TMC5241_DIAG0_DIR_SHIFT, TMC5241_DIAG_GCONF, false})
|
||
#define TMC5241_DIAG0_XCOMP_MASK 0x00000040
|
||
#define TMC5241_DIAG0_XCOMP_SHIFT 6
|
||
#define TMC5241_DIAG0_XCOMP_FIELD ((RegisterField) {TMC5241_DIAG0_XCOMP_MASK, TMC5241_DIAG0_XCOMP_SHIFT, TMC5241_DIAG_GCONF, false})
|
||
#define TMC5241_DIAG0_EV_STOP_REF_MASK 0x00000080
|
||
#define TMC5241_DIAG0_EV_STOP_REF_SHIFT 7
|
||
#define TMC5241_DIAG0_EV_STOP_REF_FIELD ((RegisterField) {TMC5241_DIAG0_EV_STOP_REF_MASK, TMC5241_DIAG0_EV_STOP_REF_SHIFT, TMC5241_DIAG_GCONF, false})
|
||
#define TMC5241_DIAG0_EV_STOP_SG_MASK 0x00000100
|
||
#define TMC5241_DIAG0_EV_STOP_SG_SHIFT 8
|
||
#define TMC5241_DIAG0_EV_STOP_SG_FIELD ((RegisterField) {TMC5241_DIAG0_EV_STOP_SG_MASK, TMC5241_DIAG0_EV_STOP_SG_SHIFT, TMC5241_DIAG_GCONF, false})
|
||
#define TMC5241_DIAG0_EV_POS_REACHED_MASK 0x00000200
|
||
#define TMC5241_DIAG0_EV_POS_REACHED_SHIFT 9
|
||
#define TMC5241_DIAG0_EV_POS_REACHED_FIELD ((RegisterField) {TMC5241_DIAG0_EV_POS_REACHED_MASK, TMC5241_DIAG0_EV_POS_REACHED_SHIFT, TMC5241_DIAG_GCONF, false})
|
||
#define TMC5241_DIAG0_EV_N_DEVIATION_MASK 0x00000400
|
||
#define TMC5241_DIAG0_EV_N_DEVIATION_SHIFT 10
|
||
#define TMC5241_DIAG0_EV_N_DEVIATION_FIELD ((RegisterField) {TMC5241_DIAG0_EV_N_DEVIATION_MASK, TMC5241_DIAG0_EV_N_DEVIATION_SHIFT, TMC5241_DIAG_GCONF, false})
|
||
#define TMC5241_DIAG0_OVERVOLTAGE_MASK 0x00000800
|
||
#define TMC5241_DIAG0_OVERVOLTAGE_SHIFT 11
|
||
#define TMC5241_DIAG0_OVERVOLTAGE_FIELD ((RegisterField) {TMC5241_DIAG0_OVERVOLTAGE_MASK, TMC5241_DIAG0_OVERVOLTAGE_SHIFT, TMC5241_DIAG_GCONF, false})
|
||
#define TMC5241_DIAG1_ERROR_MASK 0x00010000
|
||
#define TMC5241_DIAG1_ERROR_SHIFT 16
|
||
#define TMC5241_DIAG1_ERROR_FIELD ((RegisterField) {TMC5241_DIAG1_ERROR_MASK, TMC5241_DIAG1_ERROR_SHIFT, TMC5241_DIAG_GCONF, false})
|
||
#define TMC5241_DIAG1_OTPW_MASK 0x00020000
|
||
#define TMC5241_DIAG1_OTPW_SHIFT 17
|
||
#define TMC5241_DIAG1_OTPW_FIELD ((RegisterField) {TMC5241_DIAG1_OTPW_MASK, TMC5241_DIAG1_OTPW_SHIFT, TMC5241_DIAG_GCONF, false})
|
||
#define TMC5241_DIAG1_STALL_MASK 0x00040000
|
||
#define TMC5241_DIAG1_STALL_SHIFT 18
|
||
#define TMC5241_DIAG1_STALL_FIELD ((RegisterField) {TMC5241_DIAG1_STALL_MASK, TMC5241_DIAG1_STALL_SHIFT, TMC5241_DIAG_GCONF, false})
|
||
#define TMC5241_DIAG1_INDEX_MASK 0x00080000
|
||
#define TMC5241_DIAG1_INDEX_SHIFT 19
|
||
#define TMC5241_DIAG1_INDEX_FIELD ((RegisterField) {TMC5241_DIAG1_INDEX_MASK, TMC5241_DIAG1_INDEX_SHIFT, TMC5241_DIAG_GCONF, false})
|
||
#define TMC5241_DIAG1_STEP_MASK 0x00100000
|
||
#define TMC5241_DIAG1_STEP_SHIFT 20
|
||
#define TMC5241_DIAG1_STEP_FIELD ((RegisterField) {TMC5241_DIAG1_STEP_MASK, TMC5241_DIAG1_STEP_SHIFT, TMC5241_DIAG_GCONF, false})
|
||
#define TMC5241_DIAG1_DIR_MASK 0x00200000
|
||
#define TMC5241_DIAG1_DIR_SHIFT 21
|
||
#define TMC5241_DIAG1_DIR_FIELD ((RegisterField) {TMC5241_DIAG1_DIR_MASK, TMC5241_DIAG1_DIR_SHIFT, TMC5241_DIAG_GCONF, false})
|
||
#define TMC5241_DIAG1_XCOMP_MASK 0x00400000
|
||
#define TMC5241_DIAG1_XCOMP_SHIFT 22
|
||
#define TMC5241_DIAG1_XCOMP_FIELD ((RegisterField) {TMC5241_DIAG1_XCOMP_MASK, TMC5241_DIAG1_XCOMP_SHIFT, TMC5241_DIAG_GCONF, false})
|
||
#define TMC5241_DIAG1_EV_STOP_REF_MASK 0x00800000
|
||
#define TMC5241_DIAG1_EV_STOP_REF_SHIFT 23
|
||
#define TMC5241_DIAG1_EV_STOP_REF_FIELD ((RegisterField) {TMC5241_DIAG1_EV_STOP_REF_MASK, TMC5241_DIAG1_EV_STOP_REF_SHIFT, TMC5241_DIAG_GCONF, false})
|
||
#define TMC5241_DIAG1_EV_STOP_SG_MASK 0x01000000
|
||
#define TMC5241_DIAG1_EV_STOP_SG_SHIFT 24
|
||
#define TMC5241_DIAG1_EV_STOP_SG_FIELD ((RegisterField) {TMC5241_DIAG1_EV_STOP_SG_MASK, TMC5241_DIAG1_EV_STOP_SG_SHIFT, TMC5241_DIAG_GCONF, false})
|
||
#define TMC5241_DIAG1_EV_POS_REACHED_MASK 0x02000000
|
||
#define TMC5241_DIAG1_EV_POS_REACHED_SHIFT 25
|
||
#define TMC5241_DIAG1_EV_POS_REACHED_FIELD ((RegisterField) {TMC5241_DIAG1_EV_POS_REACHED_MASK, TMC5241_DIAG1_EV_POS_REACHED_SHIFT, TMC5241_DIAG_GCONF, false})
|
||
#define TMC5241_DIAG1_EV_N_DEVIATION_MASK 0x04000000
|
||
#define TMC5241_DIAG1_EV_N_DEVIATION_SHIFT 26
|
||
#define TMC5241_DIAG1_EV_N_DEVIATION_FIELD ((RegisterField) {TMC5241_DIAG1_EV_N_DEVIATION_MASK, TMC5241_DIAG1_EV_N_DEVIATION_SHIFT, TMC5241_DIAG_GCONF, false})
|
||
#define TMC5241_DIAG1_OVERVOLTAGE_MASK 0x08000000
|
||
#define TMC5241_DIAG1_OVERVOLTAGE_SHIFT 27
|
||
#define TMC5241_DIAG1_OVERVOLTAGE_FIELD ((RegisterField) {TMC5241_DIAG1_OVERVOLTAGE_MASK, TMC5241_DIAG1_OVERVOLTAGE_SHIFT, TMC5241_DIAG_GCONF, false})
|
||
#define TMC5241_CURRENT_RANGE_MASK 0x00000003
|
||
#define TMC5241_CURRENT_RANGE_SHIFT 0
|
||
#define TMC5241_CURRENT_RANGE_FIELD ((RegisterField) {TMC5241_CURRENT_RANGE_MASK, TMC5241_CURRENT_RANGE_SHIFT, TMC5241_DRV_CONF, false})
|
||
#define TMC5241_SLOPE_CONTROL_MASK 0x00000030
|
||
#define TMC5241_SLOPE_CONTROL_SHIFT 4
|
||
#define TMC5241_SLOPE_CONTROL_FIELD ((RegisterField) {TMC5241_SLOPE_CONTROL_MASK, TMC5241_SLOPE_CONTROL_SHIFT, TMC5241_DRV_CONF, false})
|
||
#define TMC5241_GLOBAL_SCALER_MASK 0x000000FF
|
||
#define TMC5241_GLOBAL_SCALER_SHIFT 0
|
||
#define TMC5241_GLOBAL_SCALER_FIELD ((RegisterField) {TMC5241_GLOBAL_SCALER_MASK, TMC5241_GLOBAL_SCALER_SHIFT, TMC5241_GLOBAL_SCALER, false})
|
||
#define TMC5241_IHOLD_MASK 0x0000001F
|
||
#define TMC5241_IHOLD_SHIFT 0
|
||
#define TMC5241_IHOLD_FIELD ((RegisterField) {TMC5241_IHOLD_MASK, TMC5241_IHOLD_SHIFT, TMC5241_IHOLD_IRUN, false})
|
||
#define TMC5241_IRUN_MASK 0x00001F00
|
||
#define TMC5241_IRUN_SHIFT 8
|
||
#define TMC5241_IRUN_FIELD ((RegisterField) {TMC5241_IRUN_MASK, TMC5241_IRUN_SHIFT, TMC5241_IHOLD_IRUN, false})
|
||
#define TMC5241_IHOLDDELAY_MASK 0x000F0000
|
||
#define TMC5241_IHOLDDELAY_SHIFT 16
|
||
#define TMC5241_IHOLDDELAY_FIELD ((RegisterField) {TMC5241_IHOLDDELAY_MASK, TMC5241_IHOLDDELAY_SHIFT, TMC5241_IHOLD_IRUN, false})
|
||
#define TMC5241_IRUNDELAY_MASK 0x0F000000
|
||
#define TMC5241_IRUNDELAY_SHIFT 24
|
||
#define TMC5241_IRUNDELAY_FIELD ((RegisterField) {TMC5241_IRUNDELAY_MASK, TMC5241_IRUNDELAY_SHIFT, TMC5241_IHOLD_IRUN, false})
|
||
#define TMC5241_TPOWERDOWN_MASK 0x000000FF
|
||
#define TMC5241_TPOWERDOWN_SHIFT 0
|
||
#define TMC5241_TPOWERDOWN_FIELD ((RegisterField) {TMC5241_TPOWERDOWN_MASK, TMC5241_TPOWERDOWN_SHIFT, TMC5241_TPOWERDOWN, false})
|
||
#define TMC5241_TSTEP_MASK 0x000FFFFF
|
||
#define TMC5241_TSTEP_SHIFT 0
|
||
#define TMC5241_TSTEP_FIELD ((RegisterField) {TMC5241_TSTEP_MASK, TMC5241_TSTEP_SHIFT, TMC5241_TSTEP, false})
|
||
#define TMC5241_TPWMTHRS_MASK 0x000FFFFF
|
||
#define TMC5241_TPWMTHRS_SHIFT 0
|
||
#define TMC5241_TPWMTHRS_FIELD ((RegisterField) {TMC5241_TPWMTHRS_MASK, TMC5241_TPWMTHRS_SHIFT, TMC5241_TPWMTHRS, false})
|
||
#define TMC5241_TCOOLTHRS_MASK 0x000FFFFF
|
||
#define TMC5241_TCOOLTHRS_SHIFT 0
|
||
#define TMC5241_TCOOLTHRS_FIELD ((RegisterField) {TMC5241_TCOOLTHRS_MASK, TMC5241_TCOOLTHRS_SHIFT, TMC5241_TCOOLTHRS, false})
|
||
#define TMC5241_THIGH_MASK 0x000FFFFF
|
||
#define TMC5241_THIGH_SHIFT 0
|
||
#define TMC5241_THIGH_FIELD ((RegisterField) {TMC5241_THIGH_MASK, TMC5241_THIGH_SHIFT, TMC5241_THIGH, false})
|
||
#define TMC5241_RAMPMODE_MASK 0x00000003
|
||
#define TMC5241_RAMPMODE_SHIFT 0
|
||
#define TMC5241_RAMPMODE_FIELD ((RegisterField) {TMC5241_RAMPMODE_MASK, TMC5241_RAMPMODE_SHIFT, TMC5241_RAMPMODE, false})
|
||
#define TMC5241_XACTUAL_MASK 0xFFFFFFFF
|
||
#define TMC5241_XACTUAL_SHIFT 0
|
||
#define TMC5241_XACTUAL_FIELD ((RegisterField) {TMC5241_XACTUAL_MASK, TMC5241_XACTUAL_SHIFT, TMC5241_XACTUAL, true})
|
||
#define TMC5241_VACTUAL_MASK 0x00FFFFFF
|
||
#define TMC5241_VACTUAL_SHIFT 0
|
||
#define TMC5241_VACTUAL_FIELD ((RegisterField) {TMC5241_VACTUAL_MASK, TMC5241_VACTUAL_SHIFT, TMC5241_VACTUAL, true})
|
||
#define TMC5241_VSTART_MASK 0x0003FFFF
|
||
#define TMC5241_VSTART_SHIFT 0
|
||
#define TMC5241_VSTART_FIELD ((RegisterField) {TMC5241_VSTART_MASK, TMC5241_VSTART_SHIFT, TMC5241_VSTART, false})
|
||
#define TMC5241_A1_MASK 0x0003FFFF
|
||
#define TMC5241_A1_SHIFT 0
|
||
#define TMC5241_A1_FIELD ((RegisterField) {TMC5241_A1_MASK, TMC5241_A1_SHIFT, TMC5241_A1, false})
|
||
#define TMC5241_V1_MASK 0x000FFFFF
|
||
#define TMC5241_V1_SHIFT 0
|
||
#define TMC5241_V1_FIELD ((RegisterField) {TMC5241_V1_MASK, TMC5241_V1_SHIFT, TMC5241_V1, false})
|
||
#define TMC5241_AMAX_MASK 0x0003FFFF
|
||
#define TMC5241_AMAX_SHIFT 0
|
||
#define TMC5241_AMAX_FIELD ((RegisterField) {TMC5241_AMAX_MASK, TMC5241_AMAX_SHIFT, TMC5241_AMAX, false})
|
||
#define TMC5241_VMAX_MASK 0x007FFFFF
|
||
#define TMC5241_VMAX_SHIFT 0
|
||
#define TMC5241_VMAX_FIELD ((RegisterField) {TMC5241_VMAX_MASK, TMC5241_VMAX_SHIFT, TMC5241_VMAX, false})
|
||
#define TMC5241_DMAX_MASK 0x0003FFFF
|
||
#define TMC5241_DMAX_SHIFT 0
|
||
#define TMC5241_DMAX_FIELD ((RegisterField) {TMC5241_DMAX_MASK, TMC5241_DMAX_SHIFT, TMC5241_DMAX, false})
|
||
#define TMC5241_TVMAX_MASK 0x0000FFFF
|
||
#define TMC5241_TVMAX_SHIFT 0
|
||
#define TMC5241_TVMAX_FIELD ((RegisterField) {TMC5241_TVMAX_MASK, TMC5241_TVMAX_SHIFT, TMC5241_TVMAX, false})
|
||
#define TMC5241_D1_MASK 0x0003FFFF
|
||
#define TMC5241_D1_SHIFT 0
|
||
#define TMC5241_D1_FIELD ((RegisterField) {TMC5241_D1_MASK, TMC5241_D1_SHIFT, TMC5241_D1, false})
|
||
#define TMC5241_VSTOP_MASK 0x0003FFFF
|
||
#define TMC5241_VSTOP_SHIFT 0
|
||
#define TMC5241_VSTOP_FIELD ((RegisterField) {TMC5241_VSTOP_MASK, TMC5241_VSTOP_SHIFT, TMC5241_VSTOP, false})
|
||
#define TMC5241_TZEROWAIT_MASK 0x0000FFFF
|
||
#define TMC5241_TZEROWAIT_SHIFT 0
|
||
#define TMC5241_TZEROWAIT_FIELD ((RegisterField) {TMC5241_TZEROWAIT_MASK, TMC5241_TZEROWAIT_SHIFT, TMC5241_TZEROWAIT, false})
|
||
#define TMC5241_XTARGET_MASK 0xFFFFFFFF
|
||
#define TMC5241_XTARGET_SHIFT 0
|
||
#define TMC5241_XTARGET_FIELD ((RegisterField) {TMC5241_XTARGET_MASK, TMC5241_XTARGET_SHIFT, TMC5241_XTARGET, true})
|
||
#define TMC5241_V2_MASK 0x000FFFFF
|
||
#define TMC5241_V2_SHIFT 0
|
||
#define TMC5241_V2_FIELD ((RegisterField) {TMC5241_V2_MASK, TMC5241_V2_SHIFT, TMC5241_V2, false})
|
||
#define TMC5241_A2_MASK 0x0003FFFF
|
||
#define TMC5241_A2_SHIFT 0
|
||
#define TMC5241_A2_FIELD ((RegisterField) {TMC5241_A2_MASK, TMC5241_A2_SHIFT, TMC5241_A2, false})
|
||
#define TMC5241_D2_MASK 0x0003FFFF
|
||
#define TMC5241_D2_SHIFT 0
|
||
#define TMC5241_D2_FIELD ((RegisterField) {TMC5241_D2_MASK, TMC5241_D2_SHIFT, TMC5241_D2, false})
|
||
#define TMC5241_AACTUAL_MASK 0x00FFFFFF
|
||
#define TMC5241_AACTUAL_SHIFT 0
|
||
#define TMC5241_AACTUAL_FIELD ((RegisterField) {TMC5241_AACTUAL_MASK, TMC5241_AACTUAL_SHIFT, TMC5241_AACTUAL, true})
|
||
//#define TMC5241_RESERVED_MASK 0x000000FF
|
||
//#define TMC5241_RESERVED_SHIFT 0
|
||
//#define TMC5241_RESERVED_FIELD ((RegisterField) {TMC5241_RESERVED_MASK, TMC5241_RESERVED_SHIFT, TMC5241_VDCMIN, false})
|
||
#define TMC5241_VDCMIN_MASK 0x007FFF00
|
||
#define TMC5241_VDCMIN_SHIFT 0
|
||
#define TMC5241_VDCMIN_FIELD ((RegisterField) {TMC5241_VDCMIN_MASK, TMC5241_VDCMIN_SHIFT, TMC5241_VDCMIN, false})
|
||
#define TMC5241_STOP_L_ENABLE_MASK 0x00000001
|
||
#define TMC5241_STOP_L_ENABLE_SHIFT 0
|
||
#define TMC5241_STOP_L_ENABLE_FIELD ((RegisterField) {TMC5241_STOP_L_ENABLE_MASK, TMC5241_STOP_L_ENABLE_SHIFT, TMC5241_SW_MODE, false})
|
||
#define TMC5241_STOP_R_ENABLE_MASK 0x00000002
|
||
#define TMC5241_STOP_R_ENABLE_SHIFT 1
|
||
#define TMC5241_STOP_R_ENABLE_FIELD ((RegisterField) {TMC5241_STOP_R_ENABLE_MASK, TMC5241_STOP_R_ENABLE_SHIFT, TMC5241_SW_MODE, false})
|
||
#define TMC5241_POL_STOP_L_MASK 0x00000004
|
||
#define TMC5241_POL_STOP_L_SHIFT 2
|
||
#define TMC5241_POL_STOP_L_FIELD ((RegisterField) {TMC5241_POL_STOP_L_MASK, TMC5241_POL_STOP_L_SHIFT, TMC5241_SW_MODE, false})
|
||
#define TMC5241_POL_STOP_R_MASK 0x00000008
|
||
#define TMC5241_POL_STOP_R_SHIFT 3
|
||
#define TMC5241_POL_STOP_R_FIELD ((RegisterField) {TMC5241_POL_STOP_R_MASK, TMC5241_POL_STOP_R_SHIFT, TMC5241_SW_MODE, false})
|
||
#define TMC5241_SWAP_LR_MASK 0x00000010
|
||
#define TMC5241_SWAP_LR_SHIFT 4
|
||
#define TMC5241_SWAP_LR_FIELD ((RegisterField) {TMC5241_SWAP_LR_MASK, TMC5241_SWAP_LR_SHIFT, TMC5241_SW_MODE, false})
|
||
#define TMC5241_LATCH_L_ACTIVE_MASK 0x00000020
|
||
#define TMC5241_LATCH_L_ACTIVE_SHIFT 5
|
||
#define TMC5241_LATCH_L_ACTIVE_FIELD ((RegisterField) {TMC5241_LATCH_L_ACTIVE_MASK, TMC5241_LATCH_L_ACTIVE_SHIFT, TMC5241_SW_MODE, false})
|
||
#define TMC5241_LATCH_L_INACTIVE_MASK 0x00000040
|
||
#define TMC5241_LATCH_L_INACTIVE_SHIFT 6
|
||
#define TMC5241_LATCH_L_INACTIVE_FIELD ((RegisterField) {TMC5241_LATCH_L_INACTIVE_MASK, TMC5241_LATCH_L_INACTIVE_SHIFT, TMC5241_SW_MODE, false})
|
||
#define TMC5241_LATCH_R_ACTIVE_MASK 0x00000080
|
||
#define TMC5241_LATCH_R_ACTIVE_SHIFT 7
|
||
#define TMC5241_LATCH_R_ACTIVE_FIELD ((RegisterField) {TMC5241_LATCH_R_ACTIVE_MASK, TMC5241_LATCH_R_ACTIVE_SHIFT, TMC5241_SW_MODE, false})
|
||
#define TMC5241_LATCH_R_INACTIVE_MASK 0x00000100
|
||
#define TMC5241_LATCH_R_INACTIVE_SHIFT 8
|
||
#define TMC5241_LATCH_R_INACTIVE_FIELD ((RegisterField) {TMC5241_LATCH_R_INACTIVE_MASK, TMC5241_LATCH_R_INACTIVE_SHIFT, TMC5241_SW_MODE, false})
|
||
#define TMC5241_EN_LATCH_ENCODER_MASK 0x00000200
|
||
#define TMC5241_EN_LATCH_ENCODER_SHIFT 9
|
||
#define TMC5241_EN_LATCH_ENCODER_FIELD ((RegisterField) {TMC5241_EN_LATCH_ENCODER_MASK, TMC5241_EN_LATCH_ENCODER_SHIFT, TMC5241_SW_MODE, false})
|
||
#define TMC5241_SG_STOP_MASK 0x00000400
|
||
#define TMC5241_SG_STOP_SHIFT 10
|
||
#define TMC5241_SG_STOP_FIELD ((RegisterField) {TMC5241_SG_STOP_MASK, TMC5241_SG_STOP_SHIFT, TMC5241_SW_MODE, false})
|
||
#define TMC5241_EN_SOFTSTOP_MASK 0x00000800
|
||
#define TMC5241_EN_SOFTSTOP_SHIFT 11
|
||
#define TMC5241_EN_SOFTSTOP_FIELD ((RegisterField) {TMC5241_EN_SOFTSTOP_MASK, TMC5241_EN_SOFTSTOP_SHIFT, TMC5241_SW_MODE, false})
|
||
#define TMC5241_EN_VIRTUAL_STOP_L_MASK 0x00001000
|
||
#define TMC5241_EN_VIRTUAL_STOP_L_SHIFT 12
|
||
#define TMC5241_EN_VIRTUAL_STOP_L_FIELD ((RegisterField) {TMC5241_EN_VIRTUAL_STOP_L_MASK, TMC5241_EN_VIRTUAL_STOP_L_SHIFT, TMC5241_SW_MODE, false})
|
||
#define TMC5241_EN_VIRTUAL_STOP_R_MASK 0x00002000
|
||
#define TMC5241_EN_VIRTUAL_STOP_R_SHIFT 13
|
||
#define TMC5241_EN_VIRTUAL_STOP_R_FIELD ((RegisterField) {TMC5241_EN_VIRTUAL_STOP_R_MASK, TMC5241_EN_VIRTUAL_STOP_R_SHIFT, TMC5241_SW_MODE, false})
|
||
#define TMC5241_VIRTUAL_STOP_ENC_MASK 0x00004000
|
||
#define TMC5241_VIRTUAL_STOP_ENC_SHIFT 14
|
||
#define TMC5241_VIRTUAL_STOP_ENC_FIELD ((RegisterField) {TMC5241_VIRTUAL_STOP_ENC_MASK, TMC5241_VIRTUAL_STOP_ENC_SHIFT, TMC5241_SW_MODE, false})
|
||
#define TMC5241_STATUS_STOP_L_MASK 0x00000001
|
||
#define TMC5241_STATUS_STOP_L_SHIFT 0
|
||
#define TMC5241_STATUS_STOP_L_FIELD ((RegisterField) {TMC5241_STATUS_STOP_L_MASK, TMC5241_STATUS_STOP_L_SHIFT, TMC5241_RAMP_STAT, false})
|
||
#define TMC5241_STATUS_STOP_R_MASK 0x00000002
|
||
#define TMC5241_STATUS_STOP_R_SHIFT 1
|
||
#define TMC5241_STATUS_STOP_R_FIELD ((RegisterField) {TMC5241_STATUS_STOP_R_MASK, TMC5241_STATUS_STOP_R_SHIFT, TMC5241_RAMP_STAT, false})
|
||
#define TMC5241_STATUS_LATCH_L_MASK 0x00000004
|
||
#define TMC5241_STATUS_LATCH_L_SHIFT 2
|
||
#define TMC5241_STATUS_LATCH_L_FIELD ((RegisterField) {TMC5241_STATUS_LATCH_L_MASK, TMC5241_STATUS_LATCH_L_SHIFT, TMC5241_RAMP_STAT, false})
|
||
#define TMC5241_STATUS_LATCH_R_MASK 0x00000008
|
||
#define TMC5241_STATUS_LATCH_R_SHIFT 3
|
||
#define TMC5241_STATUS_LATCH_R_FIELD ((RegisterField) {TMC5241_STATUS_LATCH_R_MASK, TMC5241_STATUS_LATCH_R_SHIFT, TMC5241_RAMP_STAT, false})
|
||
#define TMC5241_EVENT_STOP_L_MASK 0x00000010
|
||
#define TMC5241_EVENT_STOP_L_SHIFT 4
|
||
#define TMC5241_EVENT_STOP_L_FIELD ((RegisterField) {TMC5241_EVENT_STOP_L_MASK, TMC5241_EVENT_STOP_L_SHIFT, TMC5241_RAMP_STAT, false})
|
||
#define TMC5241_EVENT_STOP_R_MASK 0x00000020
|
||
#define TMC5241_EVENT_STOP_R_SHIFT 5
|
||
#define TMC5241_EVENT_STOP_R_FIELD ((RegisterField) {TMC5241_EVENT_STOP_R_MASK, TMC5241_EVENT_STOP_R_SHIFT, TMC5241_RAMP_STAT, false})
|
||
#define TMC5241_EVENT_STOP_SG_MASK 0x00000040
|
||
#define TMC5241_EVENT_STOP_SG_SHIFT 6
|
||
#define TMC5241_EVENT_STOP_SG_FIELD ((RegisterField) {TMC5241_EVENT_STOP_SG_MASK, TMC5241_EVENT_STOP_SG_SHIFT, TMC5241_RAMP_STAT, false})
|
||
#define TMC5241_EVENT_POS_REACHED_MASK 0x00000080
|
||
#define TMC5241_EVENT_POS_REACHED_SHIFT 7
|
||
#define TMC5241_EVENT_POS_REACHED_FIELD ((RegisterField) {TMC5241_EVENT_POS_REACHED_MASK, TMC5241_EVENT_POS_REACHED_SHIFT, TMC5241_RAMP_STAT, false})
|
||
#define TMC5241_VELOCITY_REACHED_MASK 0x00000100
|
||
#define TMC5241_VELOCITY_REACHED_SHIFT 8
|
||
#define TMC5241_VELOCITY_REACHED_FIELD ((RegisterField) {TMC5241_VELOCITY_REACHED_MASK, TMC5241_VELOCITY_REACHED_SHIFT, TMC5241_RAMP_STAT, false})
|
||
#define TMC5241_POSITION_REACHED_MASK 0x00000200
|
||
#define TMC5241_POSITION_REACHED_SHIFT 9
|
||
#define TMC5241_POSITION_REACHED_FIELD ((RegisterField) {TMC5241_POSITION_REACHED_MASK, TMC5241_POSITION_REACHED_SHIFT, TMC5241_RAMP_STAT, false})
|
||
#define TMC5241_VZERO_MASK 0x00000400
|
||
#define TMC5241_VZERO_SHIFT 10
|
||
#define TMC5241_VZERO_FIELD ((RegisterField) {TMC5241_VZERO_MASK, TMC5241_VZERO_SHIFT, TMC5241_RAMP_STAT, false})
|
||
#define TMC5241_T_ZEROWAIT_ACTIVE_MASK 0x00000800
|
||
#define TMC5241_T_ZEROWAIT_ACTIVE_SHIFT 11
|
||
#define TMC5241_T_ZEROWAIT_ACTIVE_FIELD ((RegisterField) {TMC5241_T_ZEROWAIT_ACTIVE_MASK, TMC5241_T_ZEROWAIT_ACTIVE_SHIFT, TMC5241_RAMP_STAT, false})
|
||
#define TMC5241_SECOND_MOVE_MASK 0x00001000
|
||
#define TMC5241_SECOND_MOVE_SHIFT 12
|
||
#define TMC5241_SECOND_MOVE_FIELD ((RegisterField) {TMC5241_SECOND_MOVE_MASK, TMC5241_SECOND_MOVE_SHIFT, TMC5241_RAMP_STAT, false})
|
||
#define TMC5241_STATUS_SG_MASK 0x00002000
|
||
#define TMC5241_STATUS_SG_SHIFT 13
|
||
#define TMC5241_STATUS_SG_FIELD ((RegisterField) {TMC5241_STATUS_SG_MASK, TMC5241_STATUS_SG_SHIFT, TMC5241_RAMP_STAT, false})
|
||
#define TMC5241_STATUS_VIRTUAL_STOP_L_MASK 0x00004000
|
||
#define TMC5241_STATUS_VIRTUAL_STOP_L_SHIFT 14
|
||
#define TMC5241_STATUS_VIRTUAL_STOP_L_FIELD ((RegisterField) {TMC5241_STATUS_VIRTUAL_STOP_L_MASK, TMC5241_STATUS_VIRTUAL_STOP_L_SHIFT, TMC5241_RAMP_STAT, false})
|
||
#define TMC5241_STATUS_VIRTUAL_STOP_R_MASK 0x00008000
|
||
#define TMC5241_STATUS_VIRTUAL_STOP_R_SHIFT 15
|
||
#define TMC5241_STATUS_VIRTUAL_STOP_R_FIELD ((RegisterField) {TMC5241_STATUS_VIRTUAL_STOP_R_MASK, TMC5241_STATUS_VIRTUAL_STOP_R_SHIFT, TMC5241_RAMP_STAT, false})
|
||
#define TMC5241_XLATCH_MASK 0xFFFFFFFF
|
||
#define TMC5241_XLATCH_SHIFT 0
|
||
#define TMC5241_XLATCH_FIELD ((RegisterField) {TMC5241_XLATCH_MASK, TMC5241_XLATCH_SHIFT, TMC5241_XLATCH, true})
|
||
#define TMC5241_POL_A_MASK 0x00000001
|
||
#define TMC5241_POL_A_SHIFT 0
|
||
#define TMC5241_POL_A_FIELD ((RegisterField) {TMC5241_POL_A_MASK, TMC5241_POL_A_SHIFT, TMC5241_ENCMODE, false})
|
||
#define TMC5241_POL_B_MASK 0x00000002
|
||
#define TMC5241_POL_B_SHIFT 1
|
||
#define TMC5241_POL_B_FIELD ((RegisterField) {TMC5241_POL_B_MASK, TMC5241_POL_B_SHIFT, TMC5241_ENCMODE, false})
|
||
#define TMC5241_POL_N_MASK 0x00000004
|
||
#define TMC5241_POL_N_SHIFT 2
|
||
#define TMC5241_POL_N_FIELD ((RegisterField) {TMC5241_POL_N_MASK, TMC5241_POL_N_SHIFT, TMC5241_ENCMODE, false})
|
||
#define TMC5241_IGNORE_AB_MASK 0x00000008
|
||
#define TMC5241_IGNORE_AB_SHIFT 3
|
||
#define TMC5241_IGNORE_AB_FIELD ((RegisterField) {TMC5241_IGNORE_AB_MASK, TMC5241_IGNORE_AB_SHIFT, TMC5241_ENCMODE, false})
|
||
#define TMC5241_CLR_CONT_MASK 0x00000010
|
||
#define TMC5241_CLR_CONT_SHIFT 4
|
||
#define TMC5241_CLR_CONT_FIELD ((RegisterField) {TMC5241_CLR_CONT_MASK, TMC5241_CLR_CONT_SHIFT, TMC5241_ENCMODE, false})
|
||
#define TMC5241_CLR_ONCE_MASK 0x00000020
|
||
#define TMC5241_CLR_ONCE_SHIFT 5
|
||
#define TMC5241_CLR_ONCE_FIELD ((RegisterField) {TMC5241_CLR_ONCE_MASK, TMC5241_CLR_ONCE_SHIFT, TMC5241_ENCMODE, false})
|
||
#define TMC5241_POS_NEG_EDGE_MASK 0x000000C0
|
||
#define TMC5241_POS_NEG_EDGE_SHIFT 6
|
||
#define TMC5241_POS_NEG_EDGE_FIELD ((RegisterField) {TMC5241_POS_NEG_EDGE_MASK, TMC5241_POS_NEG_EDGE_SHIFT, TMC5241_ENCMODE, false})
|
||
#define TMC5241_CLR_ENC_X_MASK 0x00000100
|
||
#define TMC5241_CLR_ENC_X_SHIFT 8
|
||
#define TMC5241_CLR_ENC_X_FIELD ((RegisterField) {TMC5241_CLR_ENC_X_MASK, TMC5241_CLR_ENC_X_SHIFT, TMC5241_ENCMODE, false})
|
||
#define TMC5241_LATCH_X_ACT_MASK 0x00000200
|
||
#define TMC5241_LATCH_X_ACT_SHIFT 9
|
||
#define TMC5241_LATCH_X_ACT_FIELD ((RegisterField) {TMC5241_LATCH_X_ACT_MASK, TMC5241_LATCH_X_ACT_SHIFT, TMC5241_ENCMODE, false})
|
||
#define TMC5241_ENC_SEL_DECIMAL_MASK 0x00000400
|
||
#define TMC5241_ENC_SEL_DECIMAL_SHIFT 10
|
||
#define TMC5241_ENC_SEL_DECIMAL_FIELD ((RegisterField) {TMC5241_ENC_SEL_DECIMAL_MASK, TMC5241_ENC_SEL_DECIMAL_SHIFT, TMC5241_ENCMODE, false})
|
||
#define TMC5241_X_ENC_MASK 0xFFFFFFFF
|
||
#define TMC5241_X_ENC_SHIFT 0
|
||
#define TMC5241_X_ENC_FIELD ((RegisterField) {TMC5241_X_ENC_MASK, TMC5241_X_ENC_SHIFT, TMC5241_X_ENC, true})
|
||
#define TMC5241_ENC_CONST_MASK 0xFFFFFFFF
|
||
#define TMC5241_ENC_CONST_SHIFT 0
|
||
#define TMC5241_ENC_CONST_FIELD ((RegisterField) {TMC5241_ENC_CONST_MASK, TMC5241_ENC_CONST_SHIFT, TMC5241_ENC_CONST, true})
|
||
#define TMC5241_N_EVENT_MASK 0x00000001
|
||
#define TMC5241_N_EVENT_SHIFT 0
|
||
#define TMC5241_N_EVENT_FIELD ((RegisterField) {TMC5241_N_EVENT_MASK, TMC5241_N_EVENT_SHIFT, TMC5241_ENC_STATUS, false})
|
||
#define TMC5241_DEVIATION_WARN_MASK 0x00000002
|
||
#define TMC5241_DEVIATION_WARN_SHIFT 1
|
||
#define TMC5241_DEVIATION_WARN_FIELD ((RegisterField) {TMC5241_DEVIATION_WARN_MASK, TMC5241_DEVIATION_WARN_SHIFT, TMC5241_ENC_STATUS, false})
|
||
#define TMC5241_ENC_LATCH_MASK 0xFFFFFFFF
|
||
#define TMC5241_ENC_LATCH_SHIFT 0
|
||
#define TMC5241_ENC_LATCH_FIELD ((RegisterField) {TMC5241_ENC_LATCH_MASK, TMC5241_ENC_LATCH_SHIFT, TMC5241_ENC_LATCH, false})
|
||
#define TMC5241_ENC_DEVIATION_MASK 0x000FFFFF
|
||
#define TMC5241_ENC_DEVIATION_SHIFT 0
|
||
#define TMC5241_ENC_DEVIATION_FIELD ((RegisterField) {TMC5241_ENC_DEVIATION_MASK, TMC5241_ENC_DEVIATION_SHIFT, TMC5241_ENC_DEVIATION, false})
|
||
#define TMC5241_VIRTUAL_STOP_L_MASK 0xFFFFFFFF
|
||
#define TMC5241_VIRTUAL_STOP_L_SHIFT 0
|
||
#define TMC5241_VIRTUAL_STOP_L_FIELD ((RegisterField) {TMC5241_VIRTUAL_STOP_L_MASK, TMC5241_VIRTUAL_STOP_L_SHIFT, TMC5241_VIRTUAL_STOP_L, true})
|
||
#define TMC5241_VIRTUAL_STOP_R_MASK 0xFFFFFFFF
|
||
#define TMC5241_VIRTUAL_STOP_R_SHIFT 0
|
||
#define TMC5241_VIRTUAL_STOP_R_FIELD ((RegisterField) {TMC5241_VIRTUAL_STOP_R_MASK, TMC5241_VIRTUAL_STOP_R_SHIFT, TMC5241_VIRTUAL_STOP_R, true})
|
||
#define TMC5241_ADC_VSUPPLY_MASK 0x00001FFF
|
||
#define TMC5241_ADC_VSUPPLY_SHIFT 0
|
||
#define TMC5241_ADC_VSUPPLY_FIELD ((RegisterField) {TMC5241_ADC_VSUPPLY_MASK, TMC5241_ADC_VSUPPLY_SHIFT, TMC5241_ADC_VSUPPLY_AIN, true})
|
||
#define TMC5241_ADC_AIN_MASK 0x1FFF0000
|
||
#define TMC5241_ADC_AIN_SHIFT 16
|
||
#define TMC5241_ADC_AIN_FIELD ((RegisterField) {TMC5241_ADC_AIN_MASK, TMC5241_ADC_AIN_SHIFT, TMC5241_ADC_VSUPPLY_AIN, true})
|
||
#define TMC5241_ADC_TEMP_MASK 0x00001FFF
|
||
#define TMC5241_ADC_TEMP_SHIFT 0
|
||
#define TMC5241_ADC_TEMP_FIELD ((RegisterField) {TMC5241_ADC_TEMP_MASK, TMC5241_ADC_TEMP_SHIFT, TMC5241_ADC_TEMP, true})
|
||
//#define TMC5241_RESERVED_MASK 0x1FFF0000
|
||
//#define TMC5241_RESERVED_SHIFT 16
|
||
//#define TMC5241_RESERVED_FIELD ((RegisterField) {TMC5241_RESERVED_MASK, TMC5241_RESERVED_SHIFT, TMC5241_ADC_TEMP, false})
|
||
#define TMC5241_OVERVOLTAGE_VTH_MASK 0x00001FFF
|
||
#define TMC5241_OVERVOLTAGE_VTH_SHIFT 0
|
||
#define TMC5241_OVERVOLTAGE_VTH_FIELD ((RegisterField) {TMC5241_OVERVOLTAGE_VTH_MASK, TMC5241_OVERVOLTAGE_VTH_SHIFT, TMC5241_OTW_OV_VTH, false})
|
||
#define TMC5241_OVERTEMPPREWARNING_VTH_MASK 0x1FFF0000
|
||
#define TMC5241_OVERTEMPPREWARNING_VTH_SHIFT 16
|
||
#define TMC5241_OVERTEMPPREWARNING_VTH_FIELD ((RegisterField) {TMC5241_OVERTEMPPREWARNING_VTH_MASK, TMC5241_OVERTEMPPREWARNING_VTH_SHIFT, TMC5241_OTW_OV_VTH, false})
|
||
#define TMC5241_MSLUT___MASK 0xFFFFFFFF
|
||
#define TMC5241_MSLUT___SHIFT 0
|
||
#define TMC5241_MSLUT___FIELD ((RegisterField) {TMC5241_MSLUT___MASK, TMC5241_MSLUT___SHIFT, TMC5241_MSLUT[0], false})
|
||
//#define TMC5241_MSLUT___MASK 0xFFFFFFFF
|
||
//#define TMC5241_MSLUT___SHIFT 0
|
||
//#define TMC5241_MSLUT___FIELD ((RegisterField) {TMC5241_MSLUT___MASK, TMC5241_MSLUT___SHIFT, TMC5241_MSLUT[1], false})
|
||
//#define TMC5241_MSLUT___MASK 0xFFFFFFFF
|
||
//#define TMC5241_MSLUT___SHIFT 0
|
||
//#define TMC5241_MSLUT___FIELD ((RegisterField) {TMC5241_MSLUT___MASK, TMC5241_MSLUT___SHIFT, TMC5241_MSLUT[2], false})
|
||
//#define TMC5241_MSLUT___MASK 0xFFFFFFFF
|
||
//#define TMC5241_MSLUT___SHIFT 0
|
||
//#define TMC5241_MSLUT___FIELD ((RegisterField) {TMC5241_MSLUT___MASK, TMC5241_MSLUT___SHIFT, TMC5241_MSLUT[3], false})
|
||
//#define TMC5241_MSLUT___MASK 0xFFFFFFFF
|
||
//#define TMC5241_MSLUT___SHIFT 0
|
||
//#define TMC5241_MSLUT___FIELD ((RegisterField) {TMC5241_MSLUT___MASK, TMC5241_MSLUT___SHIFT, TMC5241_MSLUT[4], false})
|
||
//#define TMC5241_MSLUT___MASK 0xFFFFFFFF
|
||
//#define TMC5241_MSLUT___SHIFT 0
|
||
//#define TMC5241_MSLUT___FIELD ((RegisterField) {TMC5241_MSLUT___MASK, TMC5241_MSLUT___SHIFT, TMC5241_MSLUT[5], false})
|
||
//#define TMC5241_MSLUT___MASK 0xFFFFFFFF
|
||
//#define TMC5241_MSLUT___SHIFT 0
|
||
//#define TMC5241_MSLUT___FIELD ((RegisterField) {TMC5241_MSLUT___MASK, TMC5241_MSLUT___SHIFT, TMC5241_MSLUT[6], false})
|
||
//#define TMC5241_MSLUT___MASK 0xFFFFFFFF
|
||
//#define TMC5241_MSLUT___SHIFT 0
|
||
//#define TMC5241_MSLUT___FIELD ((RegisterField) {TMC5241_MSLUT___MASK, TMC5241_MSLUT___SHIFT, TMC5241_MSLUT[7], false})
|
||
#define TMC5241_W0_MASK 0x00000003
|
||
#define TMC5241_W0_SHIFT 0
|
||
#define TMC5241_W0_FIELD ((RegisterField) {TMC5241_W0_MASK, TMC5241_W0_SHIFT, TMC5241_MSLUTSEL, false})
|
||
#define TMC5241_W1_MASK 0x0000000C
|
||
#define TMC5241_W1_SHIFT 2
|
||
#define TMC5241_W1_FIELD ((RegisterField) {TMC5241_W1_MASK, TMC5241_W1_SHIFT, TMC5241_MSLUTSEL, false})
|
||
#define TMC5241_W2_MASK 0x00000030
|
||
#define TMC5241_W2_SHIFT 4
|
||
#define TMC5241_W2_FIELD ((RegisterField) {TMC5241_W2_MASK, TMC5241_W2_SHIFT, TMC5241_MSLUTSEL, false})
|
||
#define TMC5241_W3_MASK 0x000000C0
|
||
#define TMC5241_W3_SHIFT 6
|
||
#define TMC5241_W3_FIELD ((RegisterField) {TMC5241_W3_MASK, TMC5241_W3_SHIFT, TMC5241_MSLUTSEL, false})
|
||
#define TMC5241_X1_MASK 0x0000FF00
|
||
#define TMC5241_X1_SHIFT 8
|
||
#define TMC5241_X1_FIELD ((RegisterField) {TMC5241_X1_MASK, TMC5241_X1_SHIFT, TMC5241_MSLUTSEL, false})
|
||
#define TMC5241_X2_MASK 0x00FF0000
|
||
#define TMC5241_X2_SHIFT 16
|
||
#define TMC5241_X2_FIELD ((RegisterField) {TMC5241_X2_MASK, TMC5241_X2_SHIFT, TMC5241_MSLUTSEL, false})
|
||
#define TMC5241_X3_MASK 0xFF000000
|
||
#define TMC5241_X3_SHIFT 24
|
||
#define TMC5241_X3_FIELD ((RegisterField) {TMC5241_X3_MASK, TMC5241_X3_SHIFT, TMC5241_MSLUTSEL, false})
|
||
#define TMC5241_START_SIN_MASK 0x000000FF
|
||
#define TMC5241_START_SIN_SHIFT 0
|
||
#define TMC5241_START_SIN_FIELD ((RegisterField) {TMC5241_START_SIN_MASK, TMC5241_START_SIN_SHIFT, TMC5241_MSLUTSTART, false})
|
||
#define TMC5241_START_SIN90_MASK 0x00FF0000
|
||
#define TMC5241_START_SIN90_SHIFT 16
|
||
#define TMC5241_START_SIN90_FIELD ((RegisterField) {TMC5241_START_SIN90_MASK, TMC5241_START_SIN90_SHIFT, TMC5241_MSLUTSTART, false})
|
||
#define TMC5241_OFFSET_SIN90_MASK 0xFF000000
|
||
#define TMC5241_OFFSET_SIN90_SHIFT 24
|
||
#define TMC5241_OFFSET_SIN90_FIELD ((RegisterField) {TMC5241_OFFSET_SIN90_MASK, TMC5241_OFFSET_SIN90_SHIFT, TMC5241_MSLUTSTART, false})
|
||
#define TMC5241_MSCNT_MASK 0x000003FF
|
||
#define TMC5241_MSCNT_SHIFT 0
|
||
#define TMC5241_MSCNT_FIELD ((RegisterField) {TMC5241_MSCNT_MASK, TMC5241_MSCNT_SHIFT, TMC5241_MSCNT, false})
|
||
#define TMC5241_CUR_B_MASK 0x000001FF
|
||
#define TMC5241_CUR_B_SHIFT 0
|
||
#define TMC5241_CUR_B_FIELD ((RegisterField) {TMC5241_CUR_B_MASK, TMC5241_CUR_B_SHIFT, TMC5241_MSCURACT, true})
|
||
#define TMC5241_CUR_A_MASK 0x01FF0000
|
||
#define TMC5241_CUR_A_SHIFT 16
|
||
#define TMC5241_CUR_A_FIELD ((RegisterField) {TMC5241_CUR_A_MASK, TMC5241_CUR_A_SHIFT, TMC5241_MSCURACT, true})
|
||
#define TMC5241_TOFF_MASK 0x0000000F
|
||
#define TMC5241_TOFF_SHIFT 0
|
||
#define TMC5241_TOFF_FIELD ((RegisterField) {TMC5241_TOFF_MASK, TMC5241_TOFF_SHIFT, TMC5241_CHOPCONF, false})
|
||
#define TMC5241_HSTRT_TFD210_MASK 0x00000070
|
||
#define TMC5241_HSTRT_TFD210_SHIFT 4
|
||
#define TMC5241_HSTRT_TFD210_FIELD ((RegisterField) {TMC5241_HSTRT_TFD210_MASK, TMC5241_HSTRT_TFD210_SHIFT, TMC5241_CHOPCONF, false})
|
||
#define TMC5241_HEND_OFFSET_MASK 0x00000780
|
||
#define TMC5241_HEND_OFFSET_SHIFT 7
|
||
#define TMC5241_HEND_OFFSET_FIELD ((RegisterField) {TMC5241_HEND_OFFSET_MASK, TMC5241_HEND_OFFSET_SHIFT, TMC5241_CHOPCONF, false})
|
||
#define TMC5241_FD3_MASK 0x00000800
|
||
#define TMC5241_FD3_SHIFT 11
|
||
#define TMC5241_FD3_FIELD ((RegisterField) {TMC5241_FD3_MASK, TMC5241_FD3_SHIFT, TMC5241_CHOPCONF, false})
|
||
#define TMC5241_DISFDCC_MASK 0x00001000
|
||
#define TMC5241_DISFDCC_SHIFT 12
|
||
#define TMC5241_DISFDCC_FIELD ((RegisterField) {TMC5241_DISFDCC_MASK, TMC5241_DISFDCC_SHIFT, TMC5241_CHOPCONF, false})
|
||
#define TMC5241_CHM_MASK 0x00004000
|
||
#define TMC5241_CHM_SHIFT 14
|
||
#define TMC5241_CHM_FIELD ((RegisterField) {TMC5241_CHM_MASK, TMC5241_CHM_SHIFT, TMC5241_CHOPCONF, false})
|
||
#define TMC5241_TBL_MASK 0x00018000
|
||
#define TMC5241_TBL_SHIFT 15
|
||
#define TMC5241_TBL_FIELD ((RegisterField) {TMC5241_TBL_MASK, TMC5241_TBL_SHIFT, TMC5241_CHOPCONF, false})
|
||
#define TMC5241_VHIGHFS_MASK 0x00040000
|
||
#define TMC5241_VHIGHFS_SHIFT 18
|
||
#define TMC5241_VHIGHFS_FIELD ((RegisterField) {TMC5241_VHIGHFS_MASK, TMC5241_VHIGHFS_SHIFT, TMC5241_CHOPCONF, false})
|
||
#define TMC5241_VHIGHCHM_MASK 0x00080000
|
||
#define TMC5241_VHIGHCHM_SHIFT 19
|
||
#define TMC5241_VHIGHCHM_FIELD ((RegisterField) {TMC5241_VHIGHCHM_MASK, TMC5241_VHIGHCHM_SHIFT, TMC5241_CHOPCONF, false})
|
||
#define TMC5241_TPFD_MASK 0x00F00000
|
||
#define TMC5241_TPFD_SHIFT 20
|
||
#define TMC5241_TPFD_FIELD ((RegisterField) {TMC5241_TPFD_MASK, TMC5241_TPFD_SHIFT, TMC5241_CHOPCONF, false})
|
||
#define TMC5241_MRES_MASK 0x0F000000
|
||
#define TMC5241_MRES_SHIFT 24
|
||
#define TMC5241_MRES_FIELD ((RegisterField) {TMC5241_MRES_MASK, TMC5241_MRES_SHIFT, TMC5241_CHOPCONF, false})
|
||
#define TMC5241_INTPOL_MASK 0x10000000
|
||
#define TMC5241_INTPOL_SHIFT 28
|
||
#define TMC5241_INTPOL_FIELD ((RegisterField) {TMC5241_INTPOL_MASK, TMC5241_INTPOL_SHIFT, TMC5241_CHOPCONF, false})
|
||
#define TMC5241_DEDGE_MASK 0x20000000
|
||
#define TMC5241_DEDGE_SHIFT 29
|
||
#define TMC5241_DEDGE_FIELD ((RegisterField) {TMC5241_DEDGE_MASK, TMC5241_DEDGE_SHIFT, TMC5241_CHOPCONF, false})
|
||
#define TMC5241_DISS2G_MASK 0x40000000
|
||
#define TMC5241_DISS2G_SHIFT 30
|
||
#define TMC5241_DISS2G_FIELD ((RegisterField) {TMC5241_DISS2G_MASK, TMC5241_DISS2G_SHIFT, TMC5241_CHOPCONF, false})
|
||
#define TMC5241_DISS2VS_MASK 0x80000000
|
||
#define TMC5241_DISS2VS_SHIFT 31
|
||
#define TMC5241_DISS2VS_FIELD ((RegisterField) {TMC5241_DISS2VS_MASK, TMC5241_DISS2VS_SHIFT, TMC5241_CHOPCONF, false})
|
||
#define TMC5241_SEMIN_MASK 0x0000000F
|
||
#define TMC5241_SEMIN_SHIFT 0
|
||
#define TMC5241_SEMIN_FIELD ((RegisterField) {TMC5241_SEMIN_MASK, TMC5241_SEMIN_SHIFT, TMC5241_COOLCONF, false})
|
||
#define TMC5241_SEUP_MASK 0x00000060
|
||
#define TMC5241_SEUP_SHIFT 5
|
||
#define TMC5241_SEUP_FIELD ((RegisterField) {TMC5241_SEUP_MASK, TMC5241_SEUP_SHIFT, TMC5241_COOLCONF, false})
|
||
#define TMC5241_SEMAX_MASK 0x00000F00
|
||
#define TMC5241_SEMAX_SHIFT 8
|
||
#define TMC5241_SEMAX_FIELD ((RegisterField) {TMC5241_SEMAX_MASK, TMC5241_SEMAX_SHIFT, TMC5241_COOLCONF, false})
|
||
#define TMC5241_SEDN_MASK 0x00006000
|
||
#define TMC5241_SEDN_SHIFT 13
|
||
#define TMC5241_SEDN_FIELD ((RegisterField) {TMC5241_SEDN_MASK, TMC5241_SEDN_SHIFT, TMC5241_COOLCONF, false})
|
||
#define TMC5241_SEIMIN_MASK 0x00008000
|
||
#define TMC5241_SEIMIN_SHIFT 15
|
||
#define TMC5241_SEIMIN_FIELD ((RegisterField) {TMC5241_SEIMIN_MASK, TMC5241_SEIMIN_SHIFT, TMC5241_COOLCONF, false})
|
||
#define TMC5241_SGT_MASK 0x007F0000
|
||
#define TMC5241_SGT_SHIFT 16
|
||
#define TMC5241_SGT_FIELD ((RegisterField) {TMC5241_SGT_MASK, TMC5241_SGT_SHIFT, TMC5241_COOLCONF, true})
|
||
#define TMC5241_SFILT_MASK 0x01000000
|
||
#define TMC5241_SFILT_SHIFT 24
|
||
#define TMC5241_SFILT_FIELD ((RegisterField) {TMC5241_SFILT_MASK, TMC5241_SFILT_SHIFT, TMC5241_COOLCONF, false})
|
||
#define TMC5241_DC_TIME_MASK 0x000003FF
|
||
#define TMC5241_DC_TIME_SHIFT 0
|
||
#define TMC5241_DC_TIME_FIELD ((RegisterField) {TMC5241_DC_TIME_MASK, TMC5241_DC_TIME_SHIFT, TMC5241_DCCTRL, false})
|
||
#define TMC5241_DC_SG_MASK 0x00FF0000
|
||
#define TMC5241_DC_SG_SHIFT 16
|
||
#define TMC5241_DC_SG_FIELD ((RegisterField) {TMC5241_DC_SG_MASK, TMC5241_DC_SG_SHIFT, TMC5241_DCCTRL, false})
|
||
#define TMC5241_SG_RESULT_MASK 0x000003FF
|
||
#define TMC5241_SG_RESULT_SHIFT 0
|
||
#define TMC5241_SG_RESULT_FIELD ((RegisterField) {TMC5241_SG_RESULT_MASK, TMC5241_SG_RESULT_SHIFT, TMC5241_DRV_STATUS, false})
|
||
#define TMC5241_S2VSA_MASK 0x00001000
|
||
#define TMC5241_S2VSA_SHIFT 12
|
||
#define TMC5241_S2VSA_FIELD ((RegisterField) {TMC5241_S2VSA_MASK, TMC5241_S2VSA_SHIFT, TMC5241_DRV_STATUS, false})
|
||
#define TMC5241_S2VSB_MASK 0x00002000
|
||
#define TMC5241_S2VSB_SHIFT 13
|
||
#define TMC5241_S2VSB_FIELD ((RegisterField) {TMC5241_S2VSB_MASK, TMC5241_S2VSB_SHIFT, TMC5241_DRV_STATUS, false})
|
||
#define TMC5241_STEALTH_MASK 0x00004000
|
||
#define TMC5241_STEALTH_SHIFT 14
|
||
#define TMC5241_STEALTH_FIELD ((RegisterField) {TMC5241_STEALTH_MASK, TMC5241_STEALTH_SHIFT, TMC5241_DRV_STATUS, false})
|
||
#define TMC5241_FSACTIVE_MASK 0x00008000
|
||
#define TMC5241_FSACTIVE_SHIFT 15
|
||
#define TMC5241_FSACTIVE_FIELD ((RegisterField) {TMC5241_FSACTIVE_MASK, TMC5241_FSACTIVE_SHIFT, TMC5241_DRV_STATUS, false})
|
||
#define TMC5241_CS_ACTUAL_MASK 0x001F0000
|
||
#define TMC5241_CS_ACTUAL_SHIFT 16
|
||
#define TMC5241_CS_ACTUAL_FIELD ((RegisterField) {TMC5241_CS_ACTUAL_MASK, TMC5241_CS_ACTUAL_SHIFT, TMC5241_DRV_STATUS, false})
|
||
#define TMC5241_STALLGUARD_MASK 0x01000000
|
||
#define TMC5241_STALLGUARD_SHIFT 24
|
||
#define TMC5241_STALLGUARD_FIELD ((RegisterField) {TMC5241_STALLGUARD_MASK, TMC5241_STALLGUARD_SHIFT, TMC5241_DRV_STATUS, false})
|
||
#define TMC5241_OT_MASK 0x02000000
|
||
#define TMC5241_OT_SHIFT 25
|
||
#define TMC5241_OT_FIELD ((RegisterField) {TMC5241_OT_MASK, TMC5241_OT_SHIFT, TMC5241_DRV_STATUS, false})
|
||
#define TMC5241_OTPW_MASK 0x04000000
|
||
#define TMC5241_OTPW_SHIFT 26
|
||
#define TMC5241_OTPW_FIELD ((RegisterField) {TMC5241_OTPW_MASK, TMC5241_OTPW_SHIFT, TMC5241_DRV_STATUS, false})
|
||
#define TMC5241_S2GA_MASK 0x08000000
|
||
#define TMC5241_S2GA_SHIFT 27
|
||
#define TMC5241_S2GA_FIELD ((RegisterField) {TMC5241_S2GA_MASK, TMC5241_S2GA_SHIFT, TMC5241_DRV_STATUS, false})
|
||
#define TMC5241_S2GB_MASK 0x10000000
|
||
#define TMC5241_S2GB_SHIFT 28
|
||
#define TMC5241_S2GB_FIELD ((RegisterField) {TMC5241_S2GB_MASK, TMC5241_S2GB_SHIFT, TMC5241_DRV_STATUS, false})
|
||
#define TMC5241_OLA_MASK 0x20000000
|
||
#define TMC5241_OLA_SHIFT 29
|
||
#define TMC5241_OLA_FIELD ((RegisterField) {TMC5241_OLA_MASK, TMC5241_OLA_SHIFT, TMC5241_DRV_STATUS, false})
|
||
#define TMC5241_OLB_MASK 0x40000000
|
||
#define TMC5241_OLB_SHIFT 30
|
||
#define TMC5241_OLB_FIELD ((RegisterField) {TMC5241_OLB_MASK, TMC5241_OLB_SHIFT, TMC5241_DRV_STATUS, false})
|
||
#define TMC5241_STST_MASK 0x80000000
|
||
#define TMC5241_STST_SHIFT 31
|
||
#define TMC5241_STST_FIELD ((RegisterField) {TMC5241_STST_MASK, TMC5241_STST_SHIFT, TMC5241_DRV_STATUS, false})
|
||
#define TMC5241_PWM_OFS_MASK 0x000000FF
|
||
#define TMC5241_PWM_OFS_SHIFT 0
|
||
#define TMC5241_PWM_OFS_FIELD ((RegisterField) {TMC5241_PWM_OFS_MASK, TMC5241_PWM_OFS_SHIFT, TMC5241_PWMCONF, false})
|
||
#define TMC5241_PWM_GRAD_MASK 0x0000FF00
|
||
#define TMC5241_PWM_GRAD_SHIFT 8
|
||
#define TMC5241_PWM_GRAD_FIELD ((RegisterField) {TMC5241_PWM_GRAD_MASK, TMC5241_PWM_GRAD_SHIFT, TMC5241_PWMCONF, false})
|
||
#define TMC5241_PWM_FREQ_MASK 0x00030000
|
||
#define TMC5241_PWM_FREQ_SHIFT 16
|
||
#define TMC5241_PWM_FREQ_FIELD ((RegisterField) {TMC5241_PWM_FREQ_MASK, TMC5241_PWM_FREQ_SHIFT, TMC5241_PWMCONF, false})
|
||
#define TMC5241_PWM_AUTOSCALE_MASK 0x00040000
|
||
#define TMC5241_PWM_AUTOSCALE_SHIFT 18
|
||
#define TMC5241_PWM_AUTOSCALE_FIELD ((RegisterField) {TMC5241_PWM_AUTOSCALE_MASK, TMC5241_PWM_AUTOSCALE_SHIFT, TMC5241_PWMCONF, false})
|
||
#define TMC5241_PWM_AUTOGRAD_MASK 0x00080000
|
||
#define TMC5241_PWM_AUTOGRAD_SHIFT 19
|
||
#define TMC5241_PWM_AUTOGRAD_FIELD ((RegisterField) {TMC5241_PWM_AUTOGRAD_MASK, TMC5241_PWM_AUTOGRAD_SHIFT, TMC5241_PWMCONF, false})
|
||
#define TMC5241_FREEWHEEL_MASK 0x00300000
|
||
#define TMC5241_FREEWHEEL_SHIFT 20
|
||
#define TMC5241_FREEWHEEL_FIELD ((RegisterField) {TMC5241_FREEWHEEL_MASK, TMC5241_FREEWHEEL_SHIFT, TMC5241_PWMCONF, false})
|
||
#define TMC5241_PWM_MEAS_SD_ENABLE_MASK 0x00400000
|
||
#define TMC5241_PWM_MEAS_SD_ENABLE_SHIFT 22
|
||
#define TMC5241_PWM_MEAS_SD_ENABLE_FIELD ((RegisterField) {TMC5241_PWM_MEAS_SD_ENABLE_MASK, TMC5241_PWM_MEAS_SD_ENABLE_SHIFT, TMC5241_PWMCONF, false})
|
||
#define TMC5241_PWM_DIS_REG_STST_MASK 0x00800000
|
||
#define TMC5241_PWM_DIS_REG_STST_SHIFT 23
|
||
#define TMC5241_PWM_DIS_REG_STST_FIELD ((RegisterField) {TMC5241_PWM_DIS_REG_STST_MASK, TMC5241_PWM_DIS_REG_STST_SHIFT, TMC5241_PWMCONF, false})
|
||
#define TMC5241_PWM_REG_MASK 0x0F000000
|
||
#define TMC5241_PWM_REG_SHIFT 24
|
||
#define TMC5241_PWM_REG_FIELD ((RegisterField) {TMC5241_PWM_REG_MASK, TMC5241_PWM_REG_SHIFT, TMC5241_PWMCONF, false})
|
||
#define TMC5241_PWM_LIM_MASK 0xF0000000
|
||
#define TMC5241_PWM_LIM_SHIFT 28
|
||
#define TMC5241_PWM_LIM_FIELD ((RegisterField) {TMC5241_PWM_LIM_MASK, TMC5241_PWM_LIM_SHIFT, TMC5241_PWMCONF, false})
|
||
#define TMC5241_PWM_SCALE_SUM_MASK 0x000003FF
|
||
#define TMC5241_PWM_SCALE_SUM_SHIFT 0
|
||
#define TMC5241_PWM_SCALE_SUM_FIELD ((RegisterField) {TMC5241_PWM_SCALE_SUM_MASK, TMC5241_PWM_SCALE_SUM_SHIFT, TMC5241_PWM_SCALE, false})
|
||
#define TMC5241_PWM_SCALE_AUTO_MASK 0x01FF0000
|
||
#define TMC5241_PWM_SCALE_AUTO_SHIFT 16
|
||
#define TMC5241_PWM_SCALE_AUTO_FIELD ((RegisterField) {TMC5241_PWM_SCALE_AUTO_MASK, TMC5241_PWM_SCALE_AUTO_SHIFT, TMC5241_PWM_SCALE, false})
|
||
#define TMC5241_PWM_OFS_AUTO_MASK 0x000000FF
|
||
#define TMC5241_PWM_OFS_AUTO_SHIFT 0
|
||
#define TMC5241_PWM_OFS_AUTO_FIELD ((RegisterField) {TMC5241_PWM_OFS_AUTO_MASK, TMC5241_PWM_OFS_AUTO_SHIFT, TMC5241_PWM_AUTO, false})
|
||
#define TMC5241_PWM_GRAD_AUTO_MASK 0x00FF0000
|
||
#define TMC5241_PWM_GRAD_AUTO_SHIFT 16
|
||
#define TMC5241_PWM_GRAD_AUTO_FIELD ((RegisterField) {TMC5241_PWM_GRAD_AUTO_MASK, TMC5241_PWM_GRAD_AUTO_SHIFT, TMC5241_PWM_AUTO, false})
|
||
#define TMC5241_SG4_THRS_MASK 0x000000FF
|
||
#define TMC5241_SG4_THRS_SHIFT 0
|
||
#define TMC5241_SG4_THRS_FIELD ((RegisterField) {TMC5241_SG4_THRS_MASK, TMC5241_SG4_THRS_SHIFT, TMC5241_SG4_THRS, false})
|
||
#define TMC5241_SG4_FILT_EN_MASK 0x00000100
|
||
#define TMC5241_SG4_FILT_EN_SHIFT 8
|
||
#define TMC5241_SG4_FILT_EN_FIELD ((RegisterField) {TMC5241_SG4_FILT_EN_MASK, TMC5241_SG4_FILT_EN_SHIFT, TMC5241_SG4_THRS, false})
|
||
#define TMC5241_SG_ANGLE_OFFSET_MASK 0x00000200
|
||
#define TMC5241_SG_ANGLE_OFFSET_SHIFT 9
|
||
#define TMC5241_SG_ANGLE_OFFSET_FIELD ((RegisterField) {TMC5241_SG_ANGLE_OFFSET_MASK, TMC5241_SG_ANGLE_OFFSET_SHIFT, TMC5241_SG4_THRS, false})
|
||
#define TMC5241_SG4_THRS_SHL_MASK 0x00000400
|
||
#define TMC5241_SG4_THRS_SHL_SHIFT 10
|
||
#define TMC5241_SG4_THRS_SHL_FIELD ((RegisterField) {TMC5241_SG4_THRS_SHL_MASK, TMC5241_SG4_THRS_SHL_SHIFT, TMC5241_SG4_THRS, false})
|
||
#define TMC5241_SG4_RESULT_MASK 0x000003FF
|
||
#define TMC5241_SG4_RESULT_SHIFT 0
|
||
#define TMC5241_SG4_RESULT_FIELD ((RegisterField) {TMC5241_SG4_RESULT_MASK, TMC5241_SG4_RESULT_SHIFT, TMC5241_SG4_RESULT, false})
|
||
#define TMC5241_SG4_IND_0_MASK 0x000000FF
|
||
#define TMC5241_SG4_IND_0_SHIFT 0
|
||
#define TMC5241_SG4_IND_0_FIELD ((RegisterField) {TMC5241_SG4_IND_0_MASK, TMC5241_SG4_IND_0_SHIFT, TMC5241_SG4_IND, false})
|
||
#define TMC5241_SG4_IND_1_MASK 0x0000FF00
|
||
#define TMC5241_SG4_IND_1_SHIFT 8
|
||
#define TMC5241_SG4_IND_1_FIELD ((RegisterField) {TMC5241_SG4_IND_1_MASK, TMC5241_SG4_IND_1_SHIFT, TMC5241_SG4_IND, false})
|
||
#define TMC5241_SG4_IND_2_MASK 0x00FF0000
|
||
#define TMC5241_SG4_IND_2_SHIFT 16
|
||
#define TMC5241_SG4_IND_2_FIELD ((RegisterField) {TMC5241_SG4_IND_2_MASK, TMC5241_SG4_IND_2_SHIFT, TMC5241_SG4_IND, false})
|
||
#define TMC5241_SG4_IND_3_MASK 0xFF000000
|
||
#define TMC5241_SG4_IND_3_SHIFT 24
|
||
#define TMC5241_SG4_IND_3_FIELD ((RegisterField) {TMC5241_SG4_IND_3_MASK, TMC5241_SG4_IND_3_SHIFT, TMC5241_SG4_IND, false})
|
||
#endif
|