/******************************************************************************* * Copyright © 2025 Analog Devices Inc. All Rights Reserved. * This software is proprietary to Analog Devices, Inc. and its licensors. *******************************************************************************/ #ifndef max22215_HW_ABSTRACTION #define max22215_HW_ABSTRACTION // Registers in MAX22215 #define MAX22215_CHIP_REV 0x00 #define MAX22215_CFG_1 0x01 #define MAX22215_CFG_2 0x02 #define MAX22215_FAULT1 0x03 #define MAX22215_FAULT2 0x04 #define MAX22215_FAULT_MASK1 0x05 #define MAX22215_FAULT_MASK2 0x06 #define MAX22215_ACTION_ENABLE 0x07 #define MAX22215_CONTROL_STS 0x08 // Fields in MAX22215 #define MAX22215_CHIP_REV_MASK 0x0000000F #define MAX22215_CHIP_REV_SHIFT 0 #define MAX22215_CHIP_REV_FIELD ((RegisterField) {MAX22215_CHIP_REV_MASK, MAX22215_CHIP_REV_SHIFT, MAX22215_CHIP_REV, false}) #define MAX22215_SR_MASK 0x03 #define MAX22215_SR_SHIFT 0 #define MAX22215_SR_FIELD ((RegisterField) {MAX22215_SR_MASK, MAX22215_SR_SHIFT, MAX22215_CFG_1, false}) #define MAX22215_GAIN_MASK 0x0C #define MAX22215_GAIN_SHIFT 2 #define MAX22215_GAIN_FIELD ((RegisterField) {MAX22215_GAIN_MASK, MAX22215_GAIN_SHIFT, MAX22215_CFG_1, false}) #define MAX22215_SW_HW_MASK 0x10 #define MAX22215_SW_HW_SHIFT 4 #define MAX22215_SW_HW_FIELD ((RegisterField) {MAX22215_SW_HW_MASK, MAX22215_SW_HW_SHIFT, MAX22215_CFG_1, false}) #define MAX22215_ODM_MASK 0x60 #define MAX22215_ODM_SHIFT 5 #define MAX22215_ODM_FIELD ((RegisterField) {MAX22215_ODM_MASK, MAX22215_ODM_SHIFT, MAX22215_CFG_1, false}) #define MAX22215_RESET_MASK 0x02 #define MAX22215_RESET_SHIFT 1 #define MAX22215_RESET_FIELD ((RegisterField) {MAX22215_RESET_MASK, MAX22215_RESET_SHIFT, MAX22215_CFG_2, false}) #define MAX22215_DEMAG_MASK 0x1C #define MAX22215_DEMAG_SHIFT 2 #define MAX22215_DEMAG_FIELD ((RegisterField) {MAX22215_DEMAG_MASK, MAX22215_DEMAG_SHIFT, MAX22215_CFG_2, false}) #define MAX22215_NSLEEP_MASK 0x20 #define MAX22215_NSLEEP_SHIFT 5 #define MAX22215_NSLEEP_FIELD ((RegisterField) {MAX22215_NSLEEP_MASK, MAX22215_NSLEEP_SHIFT, MAX22215_CFG_2, false}) #define MAX22215_DIAG_MASK 0x40 #define MAX22215_DIAG_SHIFT 6 #define MAX22215_DIAG_FIELD ((RegisterField) {MAX22215_DIAG_MASK, MAX22215_DIAG_SHIFT, MAX22215_CFG_2, false}) #define MAX22215_RLS_BRK_MASK 0x80 #define MAX22215_RLS_BRK_SHIFT 7 #define MAX22215_RLS_BRK_FIELD ((RegisterField) {MAX22215_RLS_BRK_MASK, MAX22215_RLS_BRK_SHIFT, MAX22215_CFG_2, false}) #define MAX22215_OCP0_MASK 0x01 #define MAX22215_OCP0_SHIFT 0 #define MAX22215_OCP0_FIELD ((RegisterField) {MAX22215_OCP0_MASK, MAX22215_OCP0_SHIFT, MAX22215_FAULT1, false}) #define MAX22215_OCP1_MASK 0x02 #define MAX22215_OCP1_SHIFT 1 #define MAX22215_OCP1_FIELD ((RegisterField) {MAX22215_OCP1_MASK, MAX22215_OCP1_SHIFT, MAX22215_FAULT1, false}) //#define MAX22215_OCP0_MASK 0x04 //#define MAX22215_OCP0_SHIFT 2 //#define MAX22215_OCP0_FIELD ((RegisterField) {MAX22215_OCP0_MASK, MAX22215_OCP0_SHIFT, MAX22215_FAULT1, false}) #define MAX22215_TWARN_UL_MASK 0x08 #define MAX22215_TWARN_UL_SHIFT 3 #define MAX22215_TWARN_UL_FIELD ((RegisterField) {MAX22215_TWARN_UL_MASK, MAX22215_TWARN_UL_SHIFT, MAX22215_FAULT1, false}) #define MAX22215_TSD_MASK 0x10 #define MAX22215_TSD_SHIFT 4 #define MAX22215_TSD_FIELD ((RegisterField) {MAX22215_TSD_MASK, MAX22215_TSD_SHIFT, MAX22215_FAULT1, false}) #define MAX22215_UVLO_MASK 0x20 #define MAX22215_UVLO_SHIFT 5 #define MAX22215_UVLO_FIELD ((RegisterField) {MAX22215_UVLO_MASK, MAX22215_UVLO_SHIFT, MAX22215_FAULT1, false}) #define MAX22215_UVLO5V_MASK 0x40 #define MAX22215_UVLO5V_SHIFT 6 #define MAX22215_UVLO5V_FIELD ((RegisterField) {MAX22215_UVLO5V_MASK, MAX22215_UVLO5V_SHIFT, MAX22215_FAULT1, false}) #define MAX22215_UVLOCP_MASK 0x80 #define MAX22215_UVLOCP_SHIFT 7 #define MAX22215_UVLOCP_FIELD ((RegisterField) {MAX22215_UVLOCP_MASK, MAX22215_UVLOCP_SHIFT, MAX22215_FAULT1, false}) #define MAX22215_LFD1_MASK 0x01 #define MAX22215_LFD1_SHIFT 0 #define MAX22215_LFD1_FIELD ((RegisterField) {MAX22215_LFD1_MASK, MAX22215_LFD1_SHIFT, MAX22215_FAULT2, false}) #define MAX22215_LFD2_MASK 0x02 #define MAX22215_LFD2_SHIFT 1 #define MAX22215_LFD2_FIELD ((RegisterField) {MAX22215_LFD2_MASK, MAX22215_LFD2_SHIFT, MAX22215_FAULT2, false}) #define MAX22215_SAFEDEM_MASK 0x04 #define MAX22215_SAFEDEM_SHIFT 2 #define MAX22215_SAFEDEM_FIELD ((RegisterField) {MAX22215_SAFEDEM_MASK, MAX22215_SAFEDEM_SHIFT, MAX22215_FAULT2, false}) #define MAX22215_ISM_MASK 0x08 #define MAX22215_ISM_SHIFT 3 #define MAX22215_ISM_FIELD ((RegisterField) {MAX22215_ISM_MASK, MAX22215_ISM_SHIFT, MAX22215_FAULT2, false}) #define MAX22215_ODVM_MASK 0x10 #define MAX22215_ODVM_SHIFT 4 #define MAX22215_ODVM_FIELD ((RegisterField) {MAX22215_ODVM_MASK, MAX22215_ODVM_SHIFT, MAX22215_FAULT2, false}) #define MAX22215_DVD_MASK 0x20 #define MAX22215_DVD_SHIFT 5 #define MAX22215_DVD_FIELD ((RegisterField) {MAX22215_DVD_MASK, MAX22215_DVD_SHIFT, MAX22215_FAULT2, false}) #define MAX22215_TWARN_MASK 0x40 #define MAX22215_TWARN_SHIFT 6 #define MAX22215_TWARN_FIELD ((RegisterField) {MAX22215_TWARN_MASK, MAX22215_TWARN_SHIFT, MAX22215_FAULT2, false}) #define MAX22215_LFD3_MASK 0x80 #define MAX22215_LFD3_SHIFT 7 #define MAX22215_LFD3_FIELD ((RegisterField) {MAX22215_LFD3_MASK, MAX22215_LFD3_SHIFT, MAX22215_FAULT2, false}) #define MAX22215_OCP0_MSK_MASK 0x01 #define MAX22215_OCP0_MASK_SHIFT 0 #define MAX22215_OCP0_MASK_FIELD ((RegisterField) {MAX22215_OCP0_MSK_MASK, MAX22215_OCP0_MASK_SHIFT, MAX22215_FAULT_MASK1, false}) #define MAX22215_OCP1_MSK_MASK 0x02 #define MAX22215_OCP1_MASK_SHIFT 1 #define MAX22215_OCP1_MASK_FIELD ((RegisterField) {MAX22215_OCP1_MSK_MASK, MAX22215_OCP1_MASK_SHIFT, MAX22215_FAULT_MASK1, false}) #define MAX22215_OCP2_MSK_MASK 0x04 #define MAX22215_OCP2_MASK_SHIFT 2 #define MAX22215_OCP2_MASK_FIELD ((RegisterField) {MAX22215_OCP2_MSK_MASK, MAX22215_OCP2_MASK_SHIFT, MAX22215_FAULT_MASK1, false}) #define MAX22215_TWARN_MSK_MASK 0x08 #define MAX22215_TWARN_MASK_SHIFT 3 #define MAX22215_TWARN_MASK_FIELD ((RegisterField) {MAX22215_TWARN_MSK_MASK, MAX22215_TWARN_MASK_SHIFT, MAX22215_FAULT_MASK1, false}) #define MAX22215_TSDN_MSK_MASK 0x10 #define MAX22215_TSDN_MASK_SHIFT 4 #define MAX22215_TSDN_MASK_FIELD ((RegisterField) {MAX22215_TSDN_MSK_MASK, MAX22215_TSDN_MASK_SHIFT, MAX22215_FAULT_MASK1, false}) #define MAX22215_UVLO_MSK_MASK 0x20 #define MAX22215_UVLO_MASK_SHIFT 5 #define MAX22215_UVLO_MASK_FIELD ((RegisterField) {MAX22215_UVLO_MSK_MASK, MAX22215_UVLO_MASK_SHIFT, MAX22215_FAULT_MASK1, false}) #define MAX22215_UVLO_5V_MSK_MASK 0x40 #define MAX22215_UVLO_5V_MASK_SHIFT 6 #define MAX22215_UVLO_5V_MASK_FIELD ((RegisterField) {MAX22215_UVLO_5V_MSK_MASK, MAX22215_UVLO_5V_MASK_SHIFT, MAX22215_FAULT_MASK1, false}) #define MAX22215_UVLO_CP_MSK_MASK 0x80 #define MAX22215_UVLO_CP_MASK_SHIFT 7 #define MAX22215_UVLO_CP_MASK_FIELD ((RegisterField) {MAX22215_UVLO_CP_MSK_MASK, MAX22215_UVLO_CP_MASK_SHIFT, MAX22215_FAULT_MASK1, false}) #define MAX22215_LFD1_MSK_MASK 0x01 #define MAX22215_LFD1_MASK_SHIFT 0 #define MAX22215_LFD1_MASK_FIELD ((RegisterField) {MAX22215_LFD1_MSK_MASK, MAX22215_LFD1_MASK_SHIFT, MAX22215_FAULT_MASK2, false}) #define MAX22215_LFD2_MSK_MASK 0x02 #define MAX22215_LFD2_MASK_SHIFT 1 #define MAX22215_LFD2_MASK_FIELD ((RegisterField) {MAX22215_LFD2_MSK_MASK, MAX22215_LFD2_MASK_SHIFT, MAX22215_FAULT_MASK2, false}) #define MAX22215_SAFEDEM_MSK_MASK 0x04 #define MAX22215_SAFEDEM_MASK_SHIFT 2 #define MAX22215_SAFEDEM_MASK_FIELD ((RegisterField) {MAX22215_SAFEDEM_MSK_MASK, MAX22215_SAFEDEM_MASK_SHIFT, MAX22215_FAULT_MASK2, false}) #define MAX22215_ISM_MSK_MASK 0x08 #define MAX22215_ISM_MASK_SHIFT 3 #define MAX22215_ISM_MASK_FIELD ((RegisterField) {MAX22215_ISM_MSK_MASK, MAX22215_ISM_MASK_SHIFT, MAX22215_FAULT_MASK2, false}) #define MAX22215_ODVM_MSK_MASK 0x10 #define MAX22215_ODVM_MASK_SHIFT 4 #define MAX22215_ODVM_MASK_FIELD ((RegisterField) {MAX22215_ODVM_MSK_MASK, MAX22215_ODVM_MASK_SHIFT, MAX22215_FAULT_MASK2, false}) #define MAX22215_DVD_MSK_MASK 0x20 #define MAX22215_DVD_MASK_SHIFT 5 #define MAX22215_DVD_MASK_FIELD ((RegisterField) {MAX22215_DVD_MSK_MASK, MAX22215_DVD_MASK_SHIFT, MAX22215_FAULT_MASK2, false}) //#define MAX22215_LFD1_MSK_MASK 0x80 //#define MAX22215_LFD1_MASK_SHIFT 7 //#define MAX22215_LFD1_MASK_FIELD ((RegisterField) {MAX22215_LFD1_MSK_MASK, MAX22215_LFD1_MASK_SHIFT, MAX22215_FAULT_MASK2, false}) #define MAX22215_ENABLE1_MASK 0x01 #define MAX22215_ENABLE1_SHIFT 0 #define MAX22215_ENABLE1_FIELD ((RegisterField) {MAX22215_ENABLE1_MASK, MAX22215_ENABLE1_SHIFT, MAX22215_ACTION_ENABLE, false}) #define MAX22215_ENABLE2_MASK 0x02 #define MAX22215_ENABLE2_SHIFT 1 #define MAX22215_ENABLE2_FIELD ((RegisterField) {MAX22215_ENABLE2_MASK, MAX22215_ENABLE2_SHIFT, MAX22215_ACTION_ENABLE, false}) #define MAX22215_ENABLE3_MASK 0x04 #define MAX22215_ENABLE3_SHIFT 2 #define MAX22215_ENABLE3_FIELD ((RegisterField) {MAX22215_ENABLE3_MASK, MAX22215_ENABLE3_SHIFT, MAX22215_ACTION_ENABLE, false}) #define MAX22215_ODVM_TIME_MASK 0x18 #define MAX22215_ODVM_TIME_SHIFT 3 #define MAX22215_ODVM_TIME_FIELD ((RegisterField) {MAX22215_ODVM_TIME_MASK, MAX22215_ODVM_TIME_SHIFT, MAX22215_ACTION_ENABLE, false}) #define MAX22215_STATUS_SLEEP_MASK 0x01 #define MAX22215_STATUS_SLEEP_SHIFT 0 #define MAX22215_STATUS_SLEEP_FIELD ((RegisterField) {MAX22215_STATUS_SLEEP_MASK, MAX22215_STATUS_SLEEP_SHIFT, MAX22215_CONTROL_STS, false}) #define MAX22215_STATUS_BRK_MASK 0x02 #define MAX22215_STATUS_BRK_SHIFT 1 #define MAX22215_STATUS_BRK_FIELD ((RegisterField) {MAX22215_STATUS_BRK_MASK, MAX22215_STATUS_BRK_SHIFT, MAX22215_CONTROL_STS, false}) #define MAX22215_STATUS_RLS_MASK 0x04 #define MAX22215_STATUS_RLS_SHIFT 2 #define MAX22215_STATUS_RLS_FIELD ((RegisterField) {MAX22215_STATUS_RLS_MASK, MAX22215_STATUS_RLS_SHIFT, MAX22215_CONTROL_STS, false}) #define MAX22215_STATUS_DIAG_MASK 0x08 #define MAX22215_STATUS_DIAG_SHIFT 3 #define MAX22215_STATUS_DIAG_FIELD ((RegisterField) {MAX22215_STATUS_DIAG_MASK, MAX22215_STATUS_DIAG_SHIFT, MAX22215_CONTROL_STS, false}) #define MAX22215_STATUS_ENF_DMG_MASK 0x10 #define MAX22215_STATUS_ENF_DMG_SHIFT 4 #define MAX22215_STATUS_ENF_DMG_FIELD ((RegisterField) {MAX22215_STATUS_ENF_DMG_MASK, MAX22215_STATUS_ENF_DMG_SHIFT, MAX22215_CONTROL_STS, false}) #define MAX22215_STATUS_SAFE_DMG_MASK 0x20 #define MAX22215_STATUS_SAFE_DMG_SHIFT 5 #define MAX22215_STATUS_SAFE_DMG_FIELD ((RegisterField) {MAX22215_STATUS_SAFE_DMG_MASK, MAX22215_STATUS_SAFE_DMG_SHIFT, MAX22215_CONTROL_STS, false}) #define MAX22215_STATUS_FLT_PWP_MASK 0x80 #define MAX22215_STATUS_FLT_PWP_SHIFT 7 #define MAX22215_STATUS_FLT_PWP_FIELD ((RegisterField) {MAX22215_STATUS_FLT_PWP_MASK, MAX22215_STATUS_FLT_PWP_SHIFT, MAX22215_CONTROL_STS, false}) #endif